Ahumm, are those Q1 and Q2 an attempt at a ripple reduction using a linear "capacitance amplifier" ? That won't fly in the HF path of a boost converter.
This absolutely will not achieve what you think it achieves: if ever this transistor opens fully on a load variation, and it does at startup, your boost coil voltage will rise uncontrollably, and the converter mosfet will get instantly toast. (or perhaps the NPN for that matter)
Remove this circuit, or get it after a first filter cap (knowing it will still sacrifice efficiency.)
Your current symmetrisation circuit probably has too much gain and bandwith.
I recommend slow it down to 30 Hz or so to avoid bringing both converters to oscillate against each other, and make the effect of a full deviation lower by increasing R13
Furthermore, I think SW1 and F1 are somewhat mismatched. What for is a I_hold = 5,5A in a 0,3A switch ?