-Get the evaluation board or the evaluation board data that may show the emissions.
-Compare your PCB layout to the evaluation board and account for any differences.
Of course, everything gets quieter if you slow it down Treez.
Adding gate resistance slows down the switching speed of the mosfet. This of course makes it quieter... it also increases the thermal dissipation of the mosfet and reduces the overall efficiency of the circuit.
As JoeyG says, get the eval board. If your design (without the gate resistor) is significantly noisier then your layout is wrong / poor. LT obviously didn't find the need to slug the mosfet speed in their eval.
I have a sneaking suspicion LT leaves out the gate resistor for simplicity, assuming the user knows they mean to put one in, of appropriate value. But then, I've tested several eval boards that shat out copious spikes in the ~100MHz range (i.e., some ~ns pulses every switching edge)...
Tim
I'm using the LT3752 + LT8311 (active clamp forward). The datasheet shows no resistors for the catch and forward mosfet gates, whereas the demo board DC1929AFA shows an optional resistor for the catch gate only.
After observing a lot of ringing on the swtich node, I worked on a snubber based on TI's app note "Controlling switch-node ringing in synchronous buck converters" (SLYT465).
In a meeting with LT's engineer, they said the RC snubber was the correct approach and they did not recommend using the catch gate resistor as it would hurt efficiency too much.
Adding gate resistance will provide some reduction in EMI, but at the penalty of greater heat dissipation of the MOSFET and reduced efficiency. The gate resistance will increase the rise time of the switch node waveform, so that the MOSFET will spend greater time in the transition region between the "on" state (very low resistance, Rdson) and "off state" (effectively infinite resistance for practical purposes.) The finite resistance between drain and source will give you I^2*R loss throughout the extended transition time.
I consider adding gate resistance as a last resort. There are 2 very effective approaches to consider first. First of all, try and reduce the size of the "antenna" that is doing the radiating> That means making the output loop, containing the MOSFET, inductor, Schottky diode (since you said it's a non-synchronous converter), and output capacitor(s) as tight as possible. Secondly as mentioned above, add an RC snubber between the MOSFET drain and source - or in severe cases, add 2 snubbers, with the other between the anode and cathode of the Schottky diode. The MOSFET snubber, if chosen properly, should critically-damp ringing of the switch node waveform transition when the MOSFET opens, and the diode snubber should critically-damp the ringing on the other transition. You really need a scope to measure the frequencies of the original ringing (usually around 100-200MHz), and how those frequencies change when you add in some trial snubber capacitor values with zero snubber resistances. Then the calculations in the excellent TI app noted above will allow you to select the proper R and C values for critical damping.
Edit: The other thing some people do is go to a 4-layer PCB and configure 2 of the layers as ground planes, whereby you'll effectively "bury" the radiating loop in a Faraday cage. A lot simpler and cheaper to add a snubber.