Innoswitch switching frequency

[Faringdon]

Hi
What drives the switching frequency recommendation for innoswitch3-EP seen on pg19 of its datsheet? Is it that the FET turns on very slowly (long time in the linear region) and thus in some cases switching frequency must be very low?...

Innoswitvh3-EP
https://www.power.com/sites/default/files/documents/innoswitch3-ep_family_datasheet.pdf

Its just occurring that since the fet and drive are contained in the chip, you have no control over fet gate series resistance etc.....and im beginning to wonder if its just better to use a standard controller with external fet, rather than the innoswitch.

[temperance]

1. Do you understand you're own question?
2. Did you ever try to "imagine" what would happen when turning on the switch that slow.
3. You are mixing switching freq. and MOSFET turn on time. They have noting to do with each other. (in this case)
4. If you ask this question it means you could do some research about QR flyback converter.
A starting point: https://www.ti.com/seclit/ml/slup302/slup302.pdf


Last but not least: contact the Chinese if in doubt. As you know, they do know how those things work because someone shared the secret and sacred knowledge with them.

[Faringdon]

3. You are mixing switching freq. and MOSFET turn on time. They have noting to do with each other. (in this case)

Thanks, as you know, if the turn on time is long ish, but the switching frequency is low...then this kind of helps, as the lower switching frequency lowers the switching loss.
As you know, slow drain transistion time helps common mode emc.

[temperance]

I'm glad to know that a lot of SMPS's are being developed in China. Because if you would be developing them, the world will heat up even faster.

[Jim from Chicago]

My interpretation is that the characteristics of the internal FET switch will vary based on the size of the particular device within the family, and so they have done the math on what the ideal frequency is in order to compromise between the different types of losses present. For example there is a tradeoff between Rds(on) and gate-drive losses. A larger FET will have lower Rds(on), but that comes at the cost of higher gate capacitances and thus higher gate-drive losses which will worsen as frequency increases.

https://www.ti.com/lit/an/slyt664/slyt664.pdf?ts=1681803346547&ref_url=https%253A%252F%252Fwww.google.com%252F