Severe Reverse recovery in Half Bridge SMPS

[Faringdon]

The attached is an LTspice simulation of an 860W Half Bridge SMPS. PDF schem also attached.
This converter runs open loop, and has no output inductor, instead relying on the transformer leakage inductance.
Due to the relatively high amount of primary magnetising current flowing, and the high transformer leakage inductance, this converter can suffer severe reverse recovery in the primary side (when a leg FET turns ON at the same time that  the other FET in the same leg is ‘experiencing’ diode conduction.) …This is akin to the situation seen in a Phase Shift Full Bridge converter.
Why is this converter then so popular?

[T3sl4co1l]

"Popular"

It's not..?

I certainly haven't seen anything doing that, outside of shitty car amps with no-inductor, unregulated DC-DC converters.

Perhaps you're confusing it for an LLC resonant?

Surely they don't use 3843s and logic, but some other controller instead?  What does its datasheet say?

Tim

[dmills]

I am guessing this thing feeds an audio power amp or something of the sort?
Yea, it is crap, but in that particular application it spends most of its time below 10% load, so it mostly gets away with it, the one virtue is cheapness.

Sometimes low BOM is a bigger virtue then technically good, at least as far as the client is concerned.
At least as drawn it has primary current sensing, not always a given with these, sometimes it is literally a 50% duty cycle into the gates.

[Faringdon]

Thanks, but i think these designs are popular....the reason being is that you dont need an output inductor...just the leakage in the transformer is used  to the same end.
You need some output inductance, but that little bit can come by way of eg seven torroids round the busbar as it leads to the output capacitor bank.

The attached is 565vin to 12v 300A out.....a very cheap way to do it, and very good as long as you use SiC FETs.

The only stipulation is that you must use SiC FETs.....because the high leakage  inductance causes severe reverse recovery in the primary transistors otherwise.......this is shown in the attached, one is a "Normal" half bridge smps with low leakage, and the other is a half bridge which uses a raised level of leakage inductance......just look at the reverse recovery current spikes in the one with high leakage.

...if you dont use SiC FETs then you might get away with it with a very heavily damped gate drive, big heatsinks, and low switching frequency, but SiC FETs are cheaper now so go with SiC.

Do you agree?
(LTspice and PDF attached)

[Faringdon]

Actually, what about the attached as a means of doing a Half Bridge with no reverse recovery in the primary?.....no marks for effiency, but surely a worker......any gremlins in this?
The anti parallel diodes would be SiC.

LTspice and PDF attached.

[T3sl4co1l]

How is reverse recovery big enough to warrant extra conduction loss?

At 30kHz?!

Tim

[Faringdon]

How is reverse recovery big enough to warrant extra conduction loss?

OK thanks, but that wasnt the meaning, ie i am speaking about reducing reverse recovery in the primary side of  Offline converters....reverse recovery and asyou know,  its ability to kill transistors  due to  it effectively being a short across the rail, albeit temporary