Without advanced planar transformers with the winding matching/shielding technique, the common mode effects of flybacks are exactly the problem.
Thanks, now it is getting interesting for us all.....
Two transistor Forward generally is indeed quieter than flyback, since the drain node transition is generally less in voltage...but we can remember that its "dv/dt" that actually causes the problem, so, as you well know, forwards are not "necessarily" quiter than flybacks....."a flyback with a decent snubber, etc etc...."...also, flybacks that turn on in the "valley" are quieter than other flybacks, sometimes can even be arranged to be quieter than some forwards.
And as you know, even if we have noise mitigating circuitry in with a flyback, the flyback still has the advantage of only needing one primary fet and one secondary diode.....and no high side drive...so the overall situation is that a flyback can end up being the easiest way to get low noise.....certainly, its often the cheapest way to get "low enough" common mode noise.
Then going on to the two switch flyback.....two primary fets but still only a single secondary diode......which can compete more directly with 2 tran forward for common mode noise situation.....As you know, with two switch flyback, the fet vds does not go above the input rail....as with the 2 switch forward.
A one transistor forward can be worse than a flyback for common mode noise, because its drain voltage shoots up to "2 x vin" when the fet switches off.......considering a reset winding equal to NP.
....then we move on to LLC.....resonant.....but not necessarily super quiet....if the fet cds capacitances are low, then the switching node will have super fast dv/dt between the rails...so even that can be "common mode noisy"....but with LLC, as you know, people can add capacitance across the fets to reduce dv/dt.....and then just have more dead time....having said that, few people do this. With LLC, if there is much magnetising current, ayk, then that will slew the switching node quicker, and (potentially) create more common mode noise...unless mitigated.
High power, high voltage PSFB's are known for a "modified version", whereby they have capacitance added across the FETs, so as to reduce the dv/dt of the FET off-going....and thence reduce common mode noise.
...This thread (eventuially) gets on to talk about adding caps across the fets of a PSFB...
https://www.edaboard.com/threads/phase-shift-full-bridge-smps-is-massively-over-hyped.342663/And of course, we all know that more common mode noise "generally" means more radiated noise....whereas more diff mode noise, doesnt always mean more radiated noise.
Anyway, apologies to OP.....please could you state what is it about the load that needs very low vout ripple? (if it does need that, please excuse my assumption)