Usage of polarised capacitor in parallel with non-paralised capacitor

[insanoff]

Hi there,
I am studying the user manual of an evaluation board for a charging circuit. Link to the manual is below.
One design consideration caught my eye. I would like to know what the purpose of polarised 2.2uF capacitor (C204) is when there is already a 4.7uF capacitor (C203).
Many thanks in advance!

https://www.st.com/resource/en/user_manual/um2940-getting-started-with-the-stdes7kwobc-7-kw-onboard-charger-reference-design-stmicroelectronics.pdf

[T3sl4co1l]

Compare the ESRs, and model the equivalent parallel impedance.

Also, it's not obvious where they've placed all those capacitors, but it's generally a bad idea to put multiple different values in parallel right beside each other.  If they're spread around doing local bypass, that may be okay, but that might not be necessarily either.

Tim

[TimFox]

In grad school, we had undergraduate students as cheap, yet clever, technicians.
I once hand drew a circuit (for a onesie) with analog and CMOS devices on the same Vectorboard, with +15 V and -15 V supplies.
To make the drawing less messy, I put a rectangle for each IC into the lower left-hand corner of the drawing, showing the power and ground connections, with appropriate bypass capacitors on each socket.
Actually, IIRC the drawing was explicit, showing the capacitor directly at the pins and wires from there to the power lines and ground symbol.
Invoking circuit theory, the tech substituted a single 1 uF capacitor for 10 0.1 uF capacitors.
With modern drafting, the careful location of the bypass capacitors is done at the PCB layout stage, moving the parts from a rats' nest to the neighborhoods of the devices.

[David Hess]

The parts list says C204 is 2.2uF ceramic, so the schematic symbol is wrong.

[Someone]

I am studying the user manual of an evaluation board for a charging circuit. Link to the manual is below.

Are they all populated? Evaluation boards often have extra footprints so the customers can try different solutions.

[insanoff]

The parts list says C204 is 2.2uF ceramic, so the schematic symbol is wrong.

Yes, that's right. I did not notice it. However, I still don't think it's necessary to use multiple values more than 2. Also, there is probably no reason to suspect rocket science behind reference designs. This is probably just another subjetive design approach.

[David Hess]

Yes, that's right. I did not notice it. However, I still don't think it's necessary to use multiple values more than 2. Also, there is probably no reason to suspect rocket science behind reference designs. This is probably just another subjetive design approach.

The most common case in a PDN (power distribution network) involves low value decoupling capacitors at the loads and a smaller number of larger bulk decoupling capacitors which serve to terminate the characteristic impedance of the PDN preventing reflections which would result in excessive ringing.

But there are cases where multiple local decoupling capacitors of different values at the load are required to maintain a sufficiently low impedance over a wide frequency range.

[uer166]

Yes, that's right. I did not notice it. However, I still don't think it's necessary to use multiple values more than 2. Also, there is probably no reason to suspect rocket science behind reference designs. This is probably just another subjetive design approach.

The most common case in a PDN (power distribution network) involves low value decoupling capacitors at the loads and a smaller number of larger bulk decoupling capacitors which serve to terminate the characteristic impedance of the PDN preventing reflections which would result in excessive ringing.

But there are cases where multiple local decoupling capacitors of different values at the load are required to maintain a sufficiently low impedance over a wide frequency range.

Is that still the case? I recall content about how such caps with different values close together and low ESR (think 100n + 10n ceramic caps) have parallel resonance (or anti-resonance from PDN perspective), resulting in very high impedance and a crap PDN. I'm more careful now and try to only have 100nF distributed around with same length traces to a plane, to avoid such issues.

LTSpice impedance sims also confirm that thought.

[David Hess]

But there are cases where multiple local decoupling capacitors of different values at the load are required to maintain a sufficiently low impedance over a wide frequency range.

Is that still the case? I recall content about how such caps with different values close together and low ESR (think 100n + 10n ceramic caps) have parallel resonance (or anti-resonance from PDN perspective), resulting in very high impedance and a crap PDN. I'm more careful now and try to only have 100nF distributed around with same length traces to a plane, to avoid such issues.

I have seen the same thing but I have absolutely run across it as a problem under ideal conditions with coaxial transmission lines where I *had* to use multiple 0.001, 0.01, and 0.1 microfarad ceramic capacitors in parallel when operating from 100 MHz to 1 GHz.[/quote]

Ok, Why is the forum adding text which is invisible in the text entry box?