Using Logic level FETs unecessarily in synchronous Buck?

[Faringdon]

Hi, do you know why the LM5143 (Synch Buck controller) was used for this Synch Buck spec (PMP31210 ref design)
of 20-58vin and 13.5Vout and 50A out?...

PMP31210 Ref Design:
https://www.ti.com/tool/PMP31210

Surely they should have just used the same_priced LM5119 instead?

The LM5143 has a max gate drive voltage of just 4.5V, meaning they are restricted to logic level FETs and their Rds(on)
is much higher at the 80V rating needed.
The LM5119 has a gate drive voltage up to 15V...meaning far lower Rds(on) FETs are available , and so FETs would be much cheaper.

Unfortunately we dont have an official company address, and so cant ask on the ti.com forum.
You would think they would advertise products in their suitable useage case, rather than in a totally unsuitable case?

I mean, 58Vin Synch Buck, with 700W output, and they are using a gate drive of 4.5V When they could have gone with 12V gate drive for
same price solution.

Maybe the SMPS is operated in sub zero temperature buildings and the extra heat dissipation is useful? -only plausible explanation.

PMP31210 Ref Design:
https://www.ti.com/tool/PMP31210

LM5143:
https://www.ti.com/product/LM5143

LM5119:
https://www.ti.com/product/LM5119

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As you know, the only real reason to use logic level FETs in any SMPS is that your Vin is below say 7V, and you dont want to bother with a bias booster so you just put up with logic level FETs. As you know, people are not using logic level FETs because of any advantage of them. They have no advantages over "normal" threshold FETs. Especially in a synchronous buck, logic level FETs are a poor choice, because with their low gate threshold voltage, they may get spuriously turned ON by the other FET turning ON and pulsing a current spike through the drain gate capacitance. Hot logic level FETs have a ridiculously low VGS(th)......as you know, they are a very poor choice, and one that you "put up with".

Not least is the fact that if you choose a logic level gate driver, then you are restricted to only logic level FETs...so you likely end up paying more for your FETs, and being more susceptible to FET nil-stocking.

Also, how does a logic level hi side gate driver supply (bootstrapped) in a synch buck chip ever do "UVLO" of the driver?...as you know...it cant really do it......when VGSth is that low you cant really do it....if you have a 12V gate driver, then you can have it "UVLO out" at say 7V.

Logic-level devices, also, have higher gate charge than standard-level parts of similar V(BR)DSS and RDS(on)

[David Aurora]

Hi, do you know why the LM5143 (Synch Buck controller) was used for this Synch Buck spec (PMP31210 ref design)
of 20-58vin and 13.5Vout and 50A out?...
...

Yes but we can't tell you, it's a secret.

[jc101]

Unfortunately we dont have an official company address, and so cant ask on the ti.com forum.

What? Absolute rubbish.  If you are a company you have a registered address, it is a legal requirement.  Use that.

Anyway, registering simply requires a postcode. Assuming you aren't a company just use, for example, WC2B 6NH, which is a bookable We Work space—perfectly justifiable to use. If they want the full address, it's Aviation House, 125 Kingsway London, WC2B 6NH.

Just go and ask TI, please.

[tggzzz]

Unfortunately we dont have an official company address, and so cant ask on the ti.com forum.

What? Absolute rubbish.  If you are a company you have a registered address, it is a legal requirement.  Use that.

Might it be that the only company "they" have is himself? Sad possibility.

[mtwieg]

Hi, do you know why the LM5143 (Synch Buck controller) was used for this Synch Buck spec (PMP31210 ref design)
of 20-58vin and 13.5Vout and 50A out?...

PMP31210 Ref Design:
https://www.ti.com/tool/PMP31210

Surely they should have just used the same_priced LM5119 instead?

The LM5143 has a max gate drive voltage of just 4.5V, meaning they are restricted to logic level FETs and their Rds(on)
is much higher at the 80V rating needed.
The LM5119 has a gate drive voltage up to 15V...meaning far lower Rds(on) FETs are available , and so FETs would be much cheaper.

You misunderstand the purpose of these reference designs. It doesn't mean that TI thinks this is the best chip for the application. It just means the reference design is a good way for engineers to evaluate the chip for their application. They're trying to sell all their chips, and only putting their latest and greatest stuff in reference designs doesn't help that.

Also the datasheet says the gate  5V, but can be up to 6.5V if you apply an external voltage with the VCCX pin. Still restricted in FET selection, but a big difference from 4.5V...

What? Absolute rubbish.  If you are a company you have a registered address, it is a legal requirement.  Use that.

Anyway, registering simply requires a postcode. Assuming you aren't a company just use, for example, WC2B 6NH, which is a bookable We Work space—perfectly justifiable to use. If they want the full address, it's Aviation House, 125 Kingsway London, WC2B 6NH.

Just go and ask TI, please.

I believe he was referring to an email address/domain, not a street address. A few years ago TI decided to cull their own userbase by only allowing people with "company" email addresses create new threads.

[Siwastaja]

As usual, Faringdon raises an excellent and relevant point and spam posters like jonpaul who never have anything constructive to say start trolling, trying to derail the thread. Reported to moderators.

I always wondered what these IC designers are smoking. Maybe limiting one to 5V IC process brings some manufacturing savings, and that's viable for low-enough (<30V, maybe <40V max Vin) voltage designs, because if you look at typical Vds_max=30V MOSFET, it will conduct just fine with Vgs=4.0V, even if not advertised as "logic level" (which is quite arbitrary designation, anyway).

But look at LM5143 and try to do worst-case analysis:
Vcc UVLO minimum 3.2V.
Subtract bootstrap diode Vf from that, say 0.4V for a schottky,
High-side MOSFET now has Vgs = 2.8V. Does the high-side UVLO help? No, because,
high-side UVLO = 2.4V.

This chip actually will operate and drive the MOSFETs at Vgs=2.4V in the worst case and you need to design with that number! Even for a "typical" steady-state case under lab conditions, Vgs of high-side switch will be around 4.5V.

Good luck trying to find MOSFETs with Vds=65V and low-enough Rds_on at Vgs=2.4V. Clearly the IC design is for MOSFETs rated to Vds_max=30V or so.

I have seen parts where Vcc regulator is rated with tighter tolerances close to 6V, and UVLO closer to 5V than 3V, and this you apparently can still do with the same "5V IC process" (IC gurus might shed more light to this) getting the manufacturing cost benefits. No idea why TI doesn't do that.

Now, not being Faringdon, maybe me raising the same points is acceptable: anyone has any further comments about the subject (not the OP)?

[Siwastaja]

Also the datasheet says the gate  5V, but can be up to 6.5V if you apply an external voltage with the VCCX pin.

This won't help, because such switcher becomes a timebomb without the two UVLOs (one for Vcc, one for Vbst). In other words, you do the math for Vgs=6.5V and then find out that it actually runs at Vgs=2.5V in the field, during a power-up or power-down or some other edge condition. The MOSFET you qualified for 6.5V is probably in its worst linear range at Vgs=2.5V and power dissipation two orders of magnitude above expected. Destruction happens in tens of milliseconds.

And adding those two UVLOs alongside with the external regulator becomes just ridiculous level of extra complexity; every bootstrapping half-bridge IC integrates the UVLOs for very good reasons. This part does too, but you can't adjust the voltage thresholds, and the factory settings are just too low. Therefore a reliable design requires redesigning half of the switcher IC around it using discretes, or accepting you have a design which just blows up in edge conditions.

Or finding a sanely designed part, but that requires quite some care, looking at specs like UVLO worst case minimums, and comparing them to the MOSFET specifications, and looking at worst case current limit maximums and comparing these to your inductor saturation current... Design work ain't easy!

[mtwieg]

Overall I agree with your points regarding the UVLOs. Guessing a product manager insisted the part be capable of operating with very low Vin, without considering how that would affect higher power applications.

In cases where the internal UVLO thresholds are too low for my liking, I'll implement my own UVLO on Vin. It's not exactly the same as an UVLO on the high/low side gate driver supplies, but unless you have external circuitry loading those supplies It's not necessary to directly monitor them, IMO.

[Simon]

*********************************************
As you know, the only real reason to use logic level FETs in any SMPS is that your Vin is below say 7V, and you dont want to bother with a bias booster so you just put up with logic level FETs. As you know, people are not using logic level FETs because of any advantage of them. They have no advantages over "normal" threshold FETs. Especially in a synchronous buck, logic level FETs are a poor choice, because with their low gate threshold voltage, they may get spuriously turned ON by the other FET turning ON and pulsing a current spike through the drain gate capacitance. Hot logic level FETs have a ridiculously low VGS(th)......as you know, they are a very poor choice, and one that you "put up with".

Not least is the fact that if you choose a logic level gate driver, then you are restricted to only logic level FETs...so you likely end up paying more for your FETs, and being more susceptible to FET nil-stocking.

Also, how does a logic level hi side gate driver supply (bootstrapped) in a synch buck chip ever do "UVLO" of the driver?...as you know...it cant really do it......when VGSth is that low you cant really do it....if you have a 12V gate driver, then you can have it "UVLO out" at say 7V.

Logic-level devices, also, have higher gate charge than standard-level parts of similar V(BR)DSS and RDS(on)

How do you know "I know"? the reason not to use logic level MOSFET that you don't know that I know is that as it turns on so easily it's difficult to turn it off. The gate drive voltage for fully on is the same as a normal MOSFET. A normal MOSFET is around 4V so with 10V on the gate it has 6V to overcome the miller plateau. When it is turned off there is less than 4V to overcome the miller plateau unless the driver sits on a negative rail. Now try using a MOSFET with 2V or less gate threshold and the asymmetry is even worse and turning it off takes even longer.

Anything else that you know I know but that I don't know I know? 

[schmitt trigger]

This reminds me of Donald Rumsfeld’s "There are unknown unknowns" speech.
Having said this…
I believe that “do you know” is a common Faringdon’s figure of speech, similar to his use of “do you agree”.
Instantly recognized.

[Simon]

no it's "you know" this time.

[Faringdon]

Thanks, also,
does anyone know if there is a way to find NFETs for Synchronous Bucks?...How to search them?....As you know, a NFET for a Sync Buck must have Cgd at least 100 times less than Cgs. There is no way to search based on Cgd or Cgd/Cgs.
We need them for 17-32VIN, 13V5 OUT, 30A out, and for 17-58Vin, 13v5 out and 50A out.

Do 4V5 NFETs have more or less likelihood of having Cgs/Cgd >100? (as opposed to 10V drive fets)

[Simon]

Thanks, also,
does anyone know if there is a way to find NFETs for Synchronous Bucks?...How to search them?....As you know, a NFET for a Sync Buck must have Cgd at least 100 times less than Cgs.

No I didn't know that! what matters is the gate charge required to turn it on. There are also figures I believe for the charge required to get the gate to different voltages. Basically cheap means crap as always so that is one way to weed unsuitable ones out.

in my experience the more current the MOSFET can carry the more gate charge, I can't remember how voltage tends to affect the specs. Basically I have noticed this trend which is common in life and engineering. If you multiply together all of the specs and the price you will probably end up with the the same number. in engineering we call this trade offs. If you want better characteristics in one respect you will either have to accept another characteristic not being as good or a substantial price increase.

[temperance]

.As you know, a NFET for a Sync Buck must have Cgd at least 100 times less than Cgs.

Can you clarify where you find that rule?

[Faringdon]

Thanks, i am trying to re-find the app note.
But it makes sense as then less current coming through CGD and charging up CGS...as you know its a capacitive divider....so CGD will take much more of the voltage instead of CGS , which is wanted when the fet is off and its CGS [...EDIT "VGS"] is required to be zero.

[JPortici]

Treez's word salads always make me raise my eyebrows.

I wonder if the 65V is because they use the same process of some automotive parts? (Max voltage for LIN Transceivers...) (Edit: they DO have a -Q1 part..)
Anyway i would agree that mosfet selection with these constraints is hard but not impossible. Since infineon's logic level mosfets have become so expensive, and because i DO have a couple of applications that require logic level mosfets with more than 100V Vds (no driver as switching speed is not critical) in the past 5 years i've been using nexperia's PSMN series of mosfets for many tasks.
Every couple of years the specific partnumber becomes either impossible to find or the price has increased to crazy expensive level, but at this point they have released other partnumbers in the series that might be even better (lower RDS on) sometimes they have mosfets that are conducting enough even with 3V3 at the gate, but that is more hit-and-miss.

[Simon]

Lower channel resistance also leads to higher capacitance

Thanks, i am trying to re-find the app note.
But it makes sense as then less current coming through CGD and charging up CGS...as you know its a capacitive divider....so CGD will take much more of the voltage instead of CGS , which is wanted when the fet is off and its CGS is required to be zero.

No, look for the gate charge spec. I don't pretend to be an expert but I suspect that a datasheet not giving the gate charge at a certain supply voltage may have something to hide.

You can of course simply buy samples and test them, simply charge and discharge the gate and monitor the charge discharge time with a scope. If the capacitance of the scope probe is too high and affects the reading either do a dry run with just the probe. Another way is to test the very thing that the gate charge requirement affect, how hot does the MOSFET get.

[Faringdon]

Thanks...So yes, indeed Cgd must be << Cgs. But as Simon kindly reminds, if the  d(Vgd/dt) is high then Cgd  appears to be higher since Cgd(apparent) = i.(d(Vgd)/dt). So yes, its not just Cgd that we must look at...but Qgd.  And we must review Qgd at the actual Vin. The higher that the Buck's Vin is...the lower must be the ratio of  Cgd/Cgs.
In the attached sim we see how the ringed capacitor being lower reduces the spurious turn-on of the low side FET.

And of course, tying in with the top post......Logic level FETs are much more susceptible to this spurious turn-on, simply because their Vgs(th) is so much lower. And when logic level FETs are used in Synch Bucks with Vin's > 30v,  then things just get worse and worse.

Basically if you are doing a Synch Buck with Vin  > 30V, then you really want to be throwing logic level FETs into the Bin. They are way to
susceptible to spurious turn ON when the top side FET turns ON.

But we simply dont see this said anywhere in App Notes...because the semico's want to flog their highly_invested_in Logic Level FETs.

[Simon]

when the manufacturer has given you the gate charge at a certain drain voltage they have negated the need to look at the parasitic capacitances as those are for you to estimate the charge you need but as the manufacturer tells you the charge it's a more reliable spec than the capacitance.

[temperance]

And of course, tying in with the top post......Logic level FETs are much more susceptible to this spurious turn-on, simply because their Vgs(th) is so much lower. And when logic level FETs are used in Synch Bucks with Vin's > 30v,  then things just get worse and worse.

That's all fine. But statements like "As you know Cgs must be 100 times Cgd" make no sense. There are a lot more parameters involved and app notes explaining this and other relevant matters concerning sync buck like structures in detail are available from almost every MOSFET manufacturer.

Edit: An old but still relevant book on MOSFET can be found here:
https://archive.org/details/bitsavers_siliconixdixMOSPOWERApplications_38092918

An app note with a more detailed explanation about MOSFET self turn on:
https://toshiba.semicon-storage.com/info/application_note_en_20180726_AKX00074.pdf?did=59473

[Faringdon]

when the manufacturer has given you the gate charge at a certain drain voltage they have negated the need to look at the parasitic capacitances as those are for you to estimate the charge you need but as the manufacturer tells you the charge it's a more reliable spec than the capacitance.

Thanks , yes, but what about the DMT8012LPS FET datasheet, which gives you Qgd at 40V...but supposing you are using it up to 58Vin? You cant do Q=CV because C varies with voltage in FETs.

Also, incidentally, this FET datasheet gives Qgs at 40V, but Qgs is pretty constant no matter what is the Vin of the synch Buck.
For "Qgs", the datasheet should give Vgs as the condition...but it does not.
They give QGS=6nC which corresponds to VGS = 3.1V, but it would not be used with VGS that low.

DMT8012LPS
https://www.diodes.com/assets/Datasheets/DMT8012LPS.pdf

An app note with a more detailed explanation about MOSFET self turn on:

And a big thankyou to Temperance, because Temperance has   provided an App Note which states exactly what was put forward in the top post...so you have kindly found the App Note that i had been seeking......the app note, on page 18 states....
[__QUOTE]   Selecting MOSFETs with a high Vth and a low Cgd is of primary importance.   [__UNQUOTE]

...noting that they actually state "Cgd" rather than "Qgd".

[Faringdon]

Its noteable that ti.com have two reference designs of synch bucks, which violate the "Qgd/Qgs < 1 rule".

PMP10260 uses BUK7Y6R0-60EX for bottom FET
https://www.ti.com/tool/PMP10260

PMP20818 uses CSD18534Q5A as bottom FET
https://www.ti.com/tool/PMP20818?keyMatch=PMP20818

..Both of these use bottom FETs with  Qgd/Qgs > 1

BUK7Y6R0-60EX
https://assets.nexperia.com/documents/data-sheet/BUK7Y6R0-60E.pdf

CSD18534Q5A
https://www.ti.com/lit/ds/symlink/csd18534q5a.pdf?ts=1713045698403&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FCSD18534Q5A%253FkeyMatch%253DCSD18534Q5A

[mtwieg]

Thanks...So yes, indeed Cgd must be << Cgs.

This is absolutely not a requirement. AFAIK the majority of power MOSFETs do not satisfy this spec, but they end up working fine anyways (so long as your switching speed is under control). It's only recently that FETs with Qgd<Qgs have become available (mainly GaN FETs). Of course you can make any FET meet this spec by adding your own Cgs externally...

Thanks , yes, but what about the DMT8012LPS FET datasheet, which gives you Qgd at 40V...but supposing you are using it up to 58Vin? You cant do Q=CV because C varies with voltage in FETs.

The charge ratio is what actually matters, not the capacitance ratio. The "rule" is based on the following worst-case scenario:
1. Vgs and Vds are both initially zero (therefore zero charge everywhere)
2. Vds instantaneously rises to some voltage VDS.
3. This injects charge into the gate via Cgd. In this infinitely short time, the gate driver cannot absorb any of this charge.
4. If the injected charge from the drain exceeds the part's rated Qgs, then the FET will turn on, leading to problems.
The nonlinearity of the capacitances is irrelevant to the outcome in this situation (only the nonlinearity of Qgd vs VDS matters). That's why the "rule" is Qgd<Qgs, not in terms of capacitance.

Thanks , yes, but what about the DMT8012LPS FET datasheet, which gives you Qgd at 40V...but supposing you are using it up to 58Vin? You cant do Q=CV because C varies with voltage in FETs.

Yes, most datasheets give plots of Coss/Crss vs Vds, but not Qoss/Qgd. In the past I've estimated Q by piecewise integration of the Coss/Crss curves.

[Faringdon]

Of course you can make any FET meet this spec by adding your own Cgs externally...

Thanks, yes, this is sometimes the case, but as the below doc says, it doesnt always work...
(pages 7 and 8 )
https://toshiba.semicon-storage.com/info/application_note_en_20180726_AKX00074.pdf?did=59473

AFAIK the majority of power MOSFETs do not satisfy this spec, but they end up working fine anyways (so long as your switching speed is under control)

Thanks, when you say this, are you referring to logic fets or "normal vgs(th)" fets?

I suspect "Normal fets with "Qgd/Qgs > 1" will be OK...but logic fets not ok......a logic fet can have a VGS(th) of just 0.9V, and the spurious turn on is well possible

That's why the "rule" is Qgs<Qgd, not in terms of capacitance.

I believe that was a typo, (you put it correct at top of your kindly supplied post)  as you know Qgs>Qgd is required.

AFAIK the majority of power MOSFETs do not satisfy this spec

Thanks, as you know, The "Qgd/Qgs < 1" spec is especially essential for synch buck fets which are logic level, and it would be great if digikey could incorporate "Qgd/Qgs" for its search engine.
At the moment it takes ages to find and cost_compare logic level fets for synch buck useage.

[Siwastaja]

and it would be great if digikey could incorporate "Qgd/Qgs" for its search engine.

As you can add Qgs externally, ratio is not important. What's more important is Qgd itself - the lower the better. And this is something suppliers do list, so just sort by Qgd.