Using Logic level FETs unecessarily in synchronous Buck?

[mtwieg]

Of course you can make any FET meet this spec by adding your own Cgs externally...

Thanks, yes, this is sometimes the case, but as the below doc says, it doesnt always work...
(pages 7 and 8 )
https://toshiba.semicon-storage.com/info/application_note_en_20180726_AKX00074.pdf?did=59473

They bring up a good point that adding Cgs alone may cause more harm than good. If they also increase dead time then the added Cgs will have the intended effect.

I suspect "Normal fets with "Qgd/Qgs > 1" will be OK...but logic fets not ok......a logic fet can have a VGS(th) of just 0.9V, and the spurious turn on is well possible

Qgs is the charge required to bring Vgs from zero to Vth, so it inherently accounts for Vth.

As you can add Qgs externally, ratio is not important. What's more important is Qgd itself - the lower the better. And this is something suppliers do list, so just sort by Qgd.

Agreed. Hypothetically, if a vendor offered a MOSFET with zero gate capacitance, then that wouldn't really make it worse, since you can always add capacitance yourself to increase Qgs. But one cannot reduce Qgd, so that's the parameter you should really be selecting.

[Faringdon]

They bring up a good point that adding Cgs alone may cause more harm than good. If they also increase dead time then the added Cgs will have the intended effect.

Thanks, as you know, the majority of synch buck controllers offer no facility to vary the dead times. And usually, the dead time is horrendously small...usually  15 to 40ns, so indeed, adding the external Cgs capacitor would usually not be a good fix.
Indeed, it is amazing that the dead times are made so ridiculously short...since most people will have a logic level "freewheel" fet in the synch buck...and  they will implement its drive with a series "ON" resistor, and a diode'd "OFF" resistor.....but since a hot logic level fet can be fully enhanced with just 0.5v on its gate...the "diode turn off" circuit will not work very well...and so indeed, the lower "freewheel" fet is likely to be ON when the top fet turns on.......smoke or overheating resulting.......so the whole thing is a bit of a shambles.

I bet that most synch bucks that are out there, with vin > 24V, would truthfully be more efficient if they simply threw away the lower "freewheeling fet" and put in a low voltage Schottky instead.

Also, its noteable that Qgd/Qgs must be <1,  though during spurious turn on in sync bucks, the lower FET actually has its gate shorted to ground by the driver, (and via any series resistance which would be low value)....so in fact, it makes you wonder why "Qgd/Qgs < 1" really applies in real life?

Another point, is that if you are using Normal threshold (not logic level)  fet drive, and have a PNP turn off snubber  right on the fet gate, then its going to be virtually impossible to get the shoot-through condition due to Qgd/Qgs>1.
However, this is not the case with logic level fets, since the PNP turn off wouldnt be of much use  with the gate threshold being so low...the PNP woudlnt be able to  turn on enough and in time.

[mtwieg]

Thanks, as you know, the majority of synch buck controllers offer no facility to vary the dead times. And usually, the dead time is horrendously small...usually  15 to 40ns, so indeed, adding the external Cgs capacitor would usually not be a good fix.

Deadtime can be adjusted with R/C/D components on the gates. In Toshiba's example, if they made the same changes to the top side FET's gate circuitry, and added turn-off diodes on both gate resistors, then that would likely eliminate cross conduction entirely. Even when Vth is <1V, the turn-off diodes still allow you to tune the dead time.

[Faringdon]

Thanks, and as discussed, i am wondering if all this "Qgd/Qgs<1" thing is just a hoax...because when the lower FET is held off, the Cgs is shorted out by the gate driver.
Its difficult to see how  the lower FET gate can be brought up to  the  ON threshold when the driver is shorting it to ground?

Perhaps the spurious on-coming is brought about by something else?...possibly v poor layout placing an stray inductance in the gate drive?

Unless their is significant stray L in the gate drive loop, i just cant see how spurious ON turning of the lower FET can be caused by the "Qgd/Qgs<1" philosophy?

[mtwieg]

Thanks, and as discussed, i am wondering if all this "Qgd/Qgs<1" thing is just a hoax...

It's what one would call a sufficient, but not necessary, condition.

because when the lower FET is held off, the Cgs is shorted out by the gate driver.
Its difficult to see how  the lower FET gate can be brought up to  the  ON threshold when the driver is shorting it to ground?

The Qgd<Qgs condition guarantees no turn-on even if the driver has very high impedance.

Another example of a sufficient (but not necessary) condition is Vth/Rg>Cgd*d(Vds)/dt. This guarantees no turn-on even if Cgs and Qgs are zero. In a more realistic scenario, Qgs is nonzero and Rg is not infinite, so both these conditions can be relaxed. You could try unifying them into one rule, but it would be quite messy.