Electronics > Power/Renewable Energy/EV's

Vds overshoot issue in half-bridge high speed topology

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Xenom:
Hi guys, i'm new. I hope this is the right section for this topic.
I'm building for learning purpose an high frequency general purpose inverter. I want that it can be suitable up to 230 Vac input voltage. The circuit is  basically an half bridge with two high speed power mosfet driven by two isolated drivers, driven as well by a microcontroller.

The only problem i'm experiencing is that this mosfet (SIHG22N60) has a very low rise/fall times. It is a very explosive device.
Now i'm driving the circuit with about 500 kHz with an input DC voltage of 5-20 Vdc. With 20 Vdc i get a 100 Vpk overshoot with 20 ns rise time on the Vds of the mosfets when the mosfet opens. The irradiated EMI is too high, i'm experiencing problems with the nearby devices, and i fear that this overshoot can lead to a driver / mosfet faliure if i try to increase the input voltage.

note:
- no load
- I'm working on a pcb i realized, i tried to be compact and close as possible with power and signal layout.
- I'm using film capacitors as close as possible  to the mosfets.
- I placed a snubber RC network in parallel with the drain-source of every mosfet, but it is light, i cannot increase the snubber because of the high frequency and voltage.
- I tried to modify the gate resistance but with no results.
- in attachment the waveform. Yellow the Vds, violet the Vge
Do you have any suggestion?

if you need more details tell me pls.

Thanks in advance

filssavi:
There could be a lot of problems, but let’s try to narrow it down

1- if you could post a schematic and layout examples it would be very helpfull

However assuming the purple one is a gate source voltage for the transistor, that is for sure a problem such a bad gate voltage Is asking for trouble

Also note that at 20V a 20 ns raise time is not too bad from an EMI standpoint, it is only when you have a high VDS voltage that that should become a problem

Xenom:

--- Quote from: filssavi on July 27, 2019, 05:05:42 pm ---There could be a lot of problems, but let’s try to narrow it down

1- if you could post a schematic and layout examples it would be very helpfull

However assuming the purple one is a gate source voltage for the transistor, that is for sure a problem such a bad gate voltage Is asking for trouble

Also note that at 20V a 20 ns raise time is not too bad from an EMI standpoint, it is only when you have a high VDS voltage that that should become a problem

--- End quote ---

Yes, tomorrow i'll post scheme and pcb layout.
Note that the purple (gate waveform) is dirtied by the Vds transient, and it is smoothed due to the high Rg i mounted in order to slow down the transient.

about the rise time, indeed the 20 ns is the rise time of the Vds at 150 V and more, so with a transient of about 5 V/ns.

Xenom:
Here is the power section of che circuit.

Note: i showed only the high voltage section and driving.
The half bridge power capacitors mounted are 1000 uF low ESR electrolitic, 3.3 uF film polypropilene capacitors and 680 nF smd capacitor on the bottom of the film capacitors.
Driving circuits are as close as possible to the respective mosfet.

I mounted only a single gate resistance, without the diode. I tried from 10 to 56 ohm.

filssavi:
I'm sorry but you have to try and draw a cleared schematic. because this one is extremely hard to follow,

- The component values are not always present
- Try avoid crossing unconnected wires as much as possible
- Name important nets (HV+, HV-, signal grounds, inputs, etc)
- show in some way what is mounted or not (that could just mean crossing out stuff that is not soldered)
- Space things out, no designator should be covered by another component
- The bridge legs MUST be drawn according to the usual convention with the positive terminal at the top and the negative at the bottom, and the output in the middle
- Everything must flow from left to right, that means not only the gate signals but also the power, so on the far right there should be the Half bridge output, not the input

Also most importantly, the circuit is not complete, you should show everything related to the power, as I don't know what all the unmarked lines going out of the shown section do.

Now, with all of that out of the way there are few things that I can't understand, how is the high side gate driver powered or is it bootstrap?
what are those 50 ohm resistor, RZH and RZL

anyway the purple trace on the scope is very wrong, the gate should raise to the gate drive voltage, with a speed set by the gate resistor, and then it should stay there until the other transistor is turned on, apart from a small dead time (1-2% of the period or less) just enough to be sure to avoid cross conduction, in your case the gate rises to ~15V and then the gate driver suddenly switches off

also a 500 kHz switching frequency for that mosfet is way too high (that means by at least a factor 20) as the transistors will cook to death in a matter of milliseconds. To switch 600V at 10A at those frequency you need to look at wide bangap devices, which are way more expensive, fragile (especially GaN HEMT that die for just about anything, including looking at them wrong)

Also keep in mind that even if you manage to switch those at such a frequency (at no more than 10 or 20 V of course), how will you control the resulting converter, a microcontroller is out of question as you will be hard pressed to close even a trivial current loop at 80-100 kHz (and that is with the hand optimized code ecc), that leaves you with FPGA, and frankly that is a big step up in complexity

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