What is "tail time" of this IGBT?

[Faringdon]

Hi,
We all know IGBTs have tail current, as the channel stays conducting for some 500ns after the gate voltage goes to zero...but where in the datasheet of the IGBT below  does it give the "tail time"?...ie, that time that the channel stays condcuting after gate voltage has fallen to zero?.......i dont believe its in the datasheet?....ive looked thru and thru.

IKW30N65EL5
https://www.infineon.com/dgdl/Infineon-IKW30N65EL5-DataSheet-v02_02-EN.pdf?fileId=5546d4624b0b249c014b11cd5d3c3acb

Also, if your "off" gate drive goes negative...say to -5V, then does that reduce the "tail time"?

[T3sl4co1l]

Fig. A, B shows the measurement points.

No, they do not give the time separately.

If you assume the on/off energies are equal aside from the energy lost to tail current, then 2.18 - 0.68 = 1.5mJ, and 1.5mJ / 400V = 3.75µC.  And then, how much current and time that takes is anyone's guess; if it's below the 10% point then it might look like a triangle of area 3.75µC, 3A tall so 1.25µs wide.  But we know it's actually a descending (exponential?) curve, dropping quicker at first so taking longer to reach the end.  But also we only count to some ending threshold (such as 2%) so it might not be that much longer.

If you're doing something similar enough to the conditions used to measure energy, just use the energy.

Tim

[Rod]

Figure A on page 15 defines t_d(off) + t_f, which are detailed in Figures 8, 9 and 10.

[ahbushnell]

The SiC MOSFET's don't have that problem.  It's really nice.  The prices are coming down.  I heard that Tesla uses them.

[Faringdon]

Thanks,
is it true the igbt has better resilience for breaking s/c currnt than SIC..also, does SIC have some "delicacys", whereby it just blows up because dv/dt on drain was too high......and what "too high" is is difficult to tell with sic?


Also, they are only giving tf etc for 0/15v gate drive...i wonder what it woudl be like for -10/15v?

[ahbushnell]

is it true the igbt has better resilience for breaking s/c currnt than SIC..also, does SIC have some "delicacys", whereby it just blows up because dv/dt on drain was too high......and what "too high" is is difficult to tell with sic?

Also, they are only giving tf etc for 0/15v gate drive...i wonder what it woudl be like for -10/15v?

SiC is fast.  That is good and bad.  The good part is the switching losses are much lower.  The down side is there tends to be oscillations from the fast switch.  You can control with careful board/bus layout and you can slow down the switch with higher gate resistance with some increase in switching losses.  We normally do a combination of these.

Shoot through protection (short) can be done with both devices.  It's a little easier with an IGBT.  This is done by monitoring the voltage drop on the device and if it goes up (i.e. high current) the devices in a leg are opened.  There are tech notes on this. 

The gate drive voltages should stay inside the specification.

I don't think dv/dt it's self causes failure but if there is a high peak voltage it could be a problem.  That relates to the oscillations above. 

[T3sl4co1l]

dV/dt is a failure mechanism in diodes and in MOSFETs.

Diodes, I'm not clear why.  Also it's specific to schottky, I think?

In MOSFETs, the parasitic BJT can be turned on, potentially drawing extra current during a rising edge (so, switching loss with a "tail" of recombination current), but also potentially biasing it into the pulse avalanche regime where it turns on suddenly and extremely quickly, causing device destruction.

The BJT has low hFE and is normally shorted B-E by the source contact (i.e., source and substrate are shorted together, it's right there in the symbol!).  So it takes a lot of dV/dt to couple enough current through the junction capacitance, into the bulk resistance between those (B and E) regions, to cause this effect.  Typically some thousands V/us, 10k being pretty common.

SiC is fast enough that I suppose it's an actual risk.  I don't think I've ever made Si go fast enough that it's nearly a risk.

As for faults, keep in mind SiC dies are impressively tiny -- there is very little bulk to dissipate power into, so the allowable short-circuit time may be quite short.  Si MOSFETs might withstand for 10s, even 100s of us; IGBTs typically 5-20us; SiC maybe somewhere inbetween, maybe less.  (Power GaN are even more severe still, with the full SOA barely being available for 1-2us.  Very power-dense indeed, this is no surprise.)

Note that desat detection works just fine on MOSFETs, you just may need to set the threshold voltage higher (above Rds(on,max) * Id(max)).  Been there done it.

Tim

[ahbushnell]

I have been working with large SiC MOSFET's now for six years and dv/dt has never been a problem other then noise generation.

But,  I was just reading the report below and dv/dt can cause triggering a MOSFET in a half bridge leg.  Miller capacitance couples voltage onto the gate.  It discusses this in the paper below. 

Short circuit protection can be done. Below is a report from CREE on short circuit protection.

https://cms.wolfspeed.com/app/uploads/2021/05/driving_cree_c3m_sic_mosfets_with_silicon_labs_si828x_gate_drivers_in_applications_requiring_short_circuit_protection.pdf

Andy