The functional block diagram in the datasheet shows an internal discharge FET on SS pin driven by VCC_UVLO, so it will depend on whether VCC reliably drops below the threshold after you switch off the 12V bias. Mind you, if the startup resistor is still there, even if VCC initially drops and triggers UVLO, surely VIN and VCC will rise again enough to try restart.
If this is important to your design, rather than asking here you really should be asking an actual TI FAE. And/or maybe test it for yourself.