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Why no chips to drive pulse transformers in SMPS?

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Why are the semico’s not making proper gate drive ICs for driving pulse transformers? (as attached in LTspice and jpeg).

If you are driving a hi side FET in an SMPS (eg two transistor forward), then you should not use a gate drive IC to directly drive a pulse transformer. This is because the inductive “kickback” from the leakage inductance, and magnetising inductance, will kill the gate drive IC’s output. These outputs are always  rated to “Vsdd+0.3V” and “Vdd-0.3V”, but even if you protect them with rail schottkys, the spike peaks will go above that range, and this will gradually kill that gate drive IC….eventually rendering your SMPS inoperable.
This also applies to the use of gate drive transformers for providing hi side supplies for gate drives, as in the attached.

On page 3 of this…
….we see shocking mis-use of a gate drive IC….ie, using it to directly drive a pulse transformer

On page 48 of this…
….we see the better way of doing it, ie, by interposing a pnp/npn totem pole. However, their implementation of the totem pole is poor (top NPN can saturate).

Attached shows the issues with driving pulse transformers (either for gate driving, or for provision of hi side supply)...and shows the best way to do it.

Open up any of the major vendors offline power supplies that you like.....you will not see gate drive ICs directly driving pulse transformers....you wills ee PNP/NPN totem poles.
You will not even see bootstrap drivers...since these have failure mode issues with negative Vs transitions, which cant be avoided, even with the finest layout.
You can get them working...but they will give field failures, eventually.

So why are the semico’s not getting hold of this?

What? Many gate drive chips specifially mention pulse transformer drive in the datasheet, being both designed and rated for such. The first three examples I looked up from memory, UCC3732x, IXDD414 and TC442x all have "pulse transformer drive" listed on page 1 of the datasheet.

Some parts specify a maximum voltage applied to the output pins, but the leakage and magnetizing inductances are... inductances, so they apply a current rather than a voltage, and the maximum output current is the relevant specification. For some parts, they specify the maximum diode reverse current, see the TC442x series for an example, and in this case you'd have to dimension the magnetizing inductance of the transformer to not exceed this value. This is a normal part of the design process.

Is there anything we can do to help you? You seem to be stuck trying to identify common design patterns as either "the only solution" or "universally bad", and this is rarely how real product engineering works, with compromises being the norm, and optimization being done on the system level rather than on the block level. I would recommend you take a serious look at your approach to engineering and the resulting outcomes, and at least consider alternative approaches. You have been given a lot of advice here in the past related to that, so there should be a lot of material to work from if you want to give it a try.

I think you've even shown in previous posts, the use of LT parts that communicate via pulse transformer directly to the chip, to communicate... what was it, sync rect? feedback? something.


Thanks, if you remove the protection diodes from the sim in the top post, you can see what i mean......you end up with voltage spikes on the OUT pin which are >vdd+0.3V.....these wont blow up the part straight away..but will result in those 1 or 2 year or so field failures.

We know that many consultancies hide this kind of thing.....and just put it down to ESD damaged components etc....but in truth, it is a failure mode.

I have used TC4420 like direct input to gate transformer and signal from transformer through resistor directly between gate and source of MOSFET. Honestly, gate and source was shorted by Zener diode.
This works well because it was phase shift full bridge and it always works with nearly 48% pwm cycle but also never less. Inductive kick was not a problem because  switching node always was clamped by MOSFETs parasitics diodes. Main source of matter is in capacitive coupling in GDT. This can suck or pump some charge into low voltage side.


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