Hi all,
I have a 53210A counter in nice shape but with (at least) one problem. It fails AutoCal with error "Computer calibration correction factor out of range" and Selftest with "Error 1". No trace of those erros on the manuals I have found. Interestingly, the counter is partially working. Let me explain
Depending on gate time, it can actually count up to a certain frequency. For example, with a 100mS gate time, it can go up to (almost) 5.110 000 000 00 KHz. It actually shows 0.000 000 000 00 if I reach 5.11Khz, so I can go up to 5.109 999 543 22 (that is a real frequency I have seen registered in the max register, I haven't been able to get a higer Reading due to phase noise). At that point, if I increase gate time by 1mS to 101mS, I only get dashes. If I decrease the frequency to about 5.059 404 I start to get readings again.
If I increase the gate time by x10, to 1000mS, then it will only measure up to .510 999 900 103 (actual reading, the limit seems to be now 0.511KHz). Notice that max frequency is now /10 than before.
If I decrease the gate time by /10 to 10mS, then it will count up to 51.099 835 447 6 KHz (actual reading, the limit seems to be then 51KHz. Notice that max frequency is now x10 than before.
As you can guess, the highest frequency it will count happens at 1mS gate time and it is 511 KHz.
Supply voltages are fine, as described in the almost-useless service guide. I can see no internal damage. I've checked with both internal and external 10MHz references (that should make no difference anyway).
It can measure the amplitude of the signal up to 350MHz without problem, it is just the frequency reading that seems to "overflow" somehow.
As expected, signal conditioning circuits are fine and show a nice square wave going into a CMP567 ultrafast comparator. Without schematic or block diagram (and complete lack of knowledge about how this counters works), I am stuck. There are two big FPGAS on the board, I hope they are fine (lower frequencies read OK, does that mean they are fine?)
I'd like to think that the counter has resources to measure low frequencies, which work fine, and other means to measure higher frequencies. Whether the difference is all within the FPGAs (I hope not) or in support circuitry I don't know...
If someone has a block diagram, pointers to information, or any kind of help, it will be very appreciated.
(Sorry if you saw this help request on YahooGroups too, I did try there first)
Thank you!
Roberto EB4EQA
www.rbarrios.com