The row of 6 pads below the NAND could be a JTAG or UART port, but that would require more tools (and knowledge).
I was hoping that the R/B* trick would at least prove that the SoC has basic sanity, but now this is inconclusive. I don't know how to proceed, other than dumping the flash. If you have a scope, look for some signs of activity on the address and data lines.