| Electronics > Repair |
| ADVANTEST R9211B |
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| m k:
Yes, probably a capacitor, just a left side of bottom part missing. Diag Soft Level 0 is mentioned in your earlier logic 1 picture. Its description should be just before that pictured page, section 3.2, maybe it's so brief that you've missed it. 68k CPU has a memory mapped I/O. Means that it doesn't have any dedicated I/O instruction like x86 has. 68k has 24 bit address bus, or 23, it's always a word. So highest bit defines data bus, you can check how it goes. Then there is this that defines 0101 of highest nibble. It can be one or two circuits, one is easy, just a chip with separated enable pin. Next is this 111x nibble for I/O, all of this can also be a single PAL chip. You can also forget those and concentrate to address bus directly. If highest bit is active all the program bus should be done, per the text in logic 1 picture. |
| stfjohn:
The section 3.2 is an analog portion. There is no battery in the ROM board. Perhaps the symbol indicates the electrolytic capacitor present. I noticed that one of the two LEDs present (D10) is not lit during operation (the LED in question is connected to p. 13 of the nearby 74F138 integrated circuit), while D3 is lit (probably indicating the presence of 12V voltage). |
| m k:
Beside the LED D3 are TP1 and TP8, can you follow where they go? I'm still after that boot info. Can you find those other test points and diodes? During the design process all numbers have at least been somewhere. There seem to be many of those 138 3to8 chips. Stacking them goes so that higher one is only an enable for the next level. I/O area division in earlier picture indicates 3to8 chips. Beside the 74F138 of D10 is 74F08. Second order after 5 for I/O can be simple 4 input AND, or 3x 2 input AND. Since 5E and 5F are both for I/O the last bit can be ignored. If the LED D10 is indicating something special, like it most likely is, it can be for 3rd section of I/O area, then it would be 2 after 5F. But is there something so special that an indicator LED is added, and just one for very sudden access. For work area RAM the LED can be a preselector, so 010x of 2nd highest nibble, then it would include nibble addresses 4 and 5. It can be even so that a watchdog something is written to addresses that blinks the LED and indicates that the software is not stuck or running away. |
| stfjohn:
TP1 goes directly to the GPIB connector; TP8 connects to p.2 of the TL7700 IC (4+4 pins) immediately behind the GPIB connector. |
| m k:
TL7700 is a voltage supervisor, so no boot info from there. In theory a GPIB control pin could be an async serial connection, but that's a quite a bit of a theory. Starting 68k goes so that first address is zero. So you can scope its address bus directly and tell how things go. For I/O check a 4 channel scope is enough. A23 and A22 to check it's less than 8 but more than 3. A19 and A18 to check it's more than x8, so after E2PROM. Conditional trigger wouldn't be bad either. |
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