Electronics > Repair
ADVANTEST R9211B
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stfjohn:
The only signs of life I see on the 68000 are the clock 10 Mhz at p. 15 and the signal 1 Mhz at p. 20.
m k:
The CPU is probably halted, pin 17 is down, if so then address and data are in high impedance state, so no more info from there.
But you can use it as an external trigger, if you can see few moments in history.
Even better if you can use it as a stopper.

Since the thing most likely does the same after every boot you are fine with dual channel scope.
Just stop collecting when halt goes down and check how those address lines were.
You may need to boot several times, but that is a small burden.

You can also build a simple circuit, single chip latch will do.
Pin 6 is address strobe, active low, address comes first and then _AS goes low.
So LS374 and output LEDs can be 8 bit status indicator and store the last partial address.
You also know that CRT controller is accessed, so something must blink or it doesn't work.
More complex it will become if you need to trace back unknown addresses, then this USB dongle logic analyzer is much easier.
stfjohn:
I was loaned a logic analyzer...
Photo #1 pod 0 = P. 1 (68HC000) (the remaining pins to follow).
Photo #2 pod 0 = P. 16 (68HC000) (the remaining pins to follow).
Photo #3 pod 0 = P. 50 (68HC000) (the remaining pins to follow).
Photo #4 pod 0 = P. 33 (68HC000) (the remaining pins to follow).
m k:
Picture 2 02 must be E pin 20, so pins 24 and 25 are down, interrupt is active.
Addresses A1-3 defines the interrupt, then other addresses are high, so that moment is history.
Pin 26 is high, so CPU is in supervisor mode and serving interrupts.

Picture 1 14 is clearly a clock, next is up so it's not GND.
07 is down, it can be _LDS and so 16 bit data operations.
A bit after center 08 goes down few times, those can be write cycles, same time data seems to be 0000.
A bit before center picture 2 has other supervisor data cycle, there data seems to be also 0000.
But the earlier cycle is read, so maybe there the CPU tries to clear the interrupt but fails.

Incoming data can be buffered.
Earlier block diagram indicates that only DMA controller is buffered, but those buffers should be drawn differently.
Maybe some other parts are completely missing.
stfjohn:
I'm afraid there's very little that can be done unfortunately....
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