| Electronics > Repair |
| ADVANTEST R9211B |
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| m k:
3 different chips so 3 chip select signals. Last 2 are A0 and A1. Assumption is that all 3 chips have same address signals, but CPU side connection is unknown. |
| stfjohn:
I'm not sure about the last connection (pod 15) because from the copper side it is really difficult to establish the exact connection to pin 20 of the U86. |
| m k:
No problem, we can forget them. PODs 09 to 13 are up all the time and same time POD 08 goes down. So there is a write cycle and assumed address is 5F34xx, so no chips are selected. Whether that address is right or wrong is not relevant this time. I/O map doesn't include 5F34xx, but 5F30xx is there, that's one bit off. Those steady state address lines have been bugging me all the time, but that alone is not a reason for anything. I'll start rereading old stuff and checking what old pictures are telling now. You can start doing that address line decoder thingy. First some general chip stuff. Externally controlled chips are many times intended to be stacked. Means that all but very few equal control signals are connected together between chips. The one that isn't is chip select or chip enable or something like that, other can be something like output enable. If there are multiple of those special signals they are usually for speed or narrowing needed other signals. One example is a ROM chip, being read only make it simple. First chip enable is asserted and chip start accepting addresses, many chips can do so simultaneously. Then becomes a read moment, for that a chip has an output enable pin. So all chips can be read through one data bus just by asserting individual output enable signals. Usually that goes so that all chips have same address pins connected and chip selects come through high order address decoder, maybe 3to8 line chip. 3to8 line chip is fine until wider decoding is needed, 7 address pins is already 16 3to8 line chips. (74xx138, 74xx137, 74xx131) So if you can't see those chips all around this case is probably different. 4to16 line chip would be 24 pin 74xx154 or 74xx159 and those are not present. 68000 CPU has still few extras, since it's a 16 bit machine accessing 8 bit peripherals. Means that data bus can be mixed. So for now your job is simple, just check which address pins are shorted to where. If 3to8 line chips are only few concentrate to PAL chips. If you can find connections you can continue to the other side of those chips. That address decoder must connect the actual destination chip also. You can also start backwards, but I don't know what the 8245B is, from 3rd set of I/O addresses. Other possibility is that previous 5F1Cxx, but that is also difficult. And most likely more or less all must be clear one day. If many address decoders are needed they are also chained, higher order codes the lower ones. So if you find high address lines from one decoder that is possibly the only one. 68450 DMAC _CS is 17. 82C79 keyboard controller _CS is 22. 62421 RTC has two _CS pins 15 and 2. X2864 E2PROM _CS is 20. D71054 timer _CS is 31. HD63265 FDC _CS is 10. HD63484 CRTC _CS is 5. TMS9914 GPIB _CE is 3. NS32081 FPU _SPC is 31. |
| m k:
When those connection searches start irritating too much you can do some analyzing. Leave POD 00 to 05 as they are. POD 06 63484 5 _CS CRTC POD 07 71054 31 _CS U52 timer POD 08 71054 31 _CS U67 timer POD 09 71054 31 _CS U86 timer POD 10 68450 17 _CS DMAC POD 11 62421 2 _CS0 RTC POD 12 62421 15 _CS1 RTC POD 13 32081 21 _SPC FPU POD 14 8279 22 _CS KBC POD 15 9914 3 _CE GPIB Trig POD 06 to 15 going down, one by one. We know that CRTC goes down, all others are unknown. Estimation is that many wont go down. Normally only one is allowed to go down at the time. Here both RTC pins can go down simultaneously. Some other pairs are also theoretically possible. |
| m k:
I'll continue with the idea that motherboard is fine and problem is a wrong program and so a bad ROM chip or its access. So your third task, check how data lines go, that's easier since there are less variations. Compared to others DMAC is different, it has full data bus. So you only need to check how few pins from its 2nd side goes, pins 33 to 36 should do. Block diagram has those buffers between DMAC and CPU buses. xx244 is 8 bits to one direction. xx245 is 8 bits to both directions. Those 2 block diagram blocks right of DMAC. They are also both double wide, it's 16 bits wide bus. So probably logic chips between CPU and DMAC. Then between DSP chip and euro-connectors are three logic pairs. xx175 xx245 xx244 xx374 xx374 xx245 xx374 is 8 bit latch. xx175 is 4 D-flops with Q and _Q outputs, it's possibly QD block diagram block above Advantest chip. Chips above and right of TC514256 4 bit data RAMs are most likely for their control. xx157 is 4x 2to1 line multiplexer. MB81C78 8k x8 static RAM is pictured in between DSP and bidirectional buffers, left side can go up, but can't reach the CPU. xx138 left from D10 LED can be address decoder for those RAMs. You can generally skip all these other side parts, but keep them in mind. The whole board is made by same folks and they will follow their principles. 68000 has a system for 8 bit data, it also has a system for 8 bit data of high side of its data bus that is internally moved to low side. Based on block diagram picture you should find all those upper narrow data peripheral chips connected to somewhere in CPU data line. |
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