| Electronics > Repair |
| ADVANTEST R9211B |
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| m k:
Change trace mode to single. You must get pictures where _CS POD signal goes down like POD 06. Now we know for sure that this 5E10xx address is for CRTC, all others are unknown. Addresses are possibly real, but they can't be connected if triggering POD signal is not going down. There can be other addresses that have happened before or after trigger and are now in picture. All pictures that are aborted are probably not triggered. Others have the actual happening somewhere else, possibly later in data. |
| m k:
--- Quote from: stfjohn on September 26, 2024, 03:13:14 pm ---before stabilizing. --- End quote --- Ok, my bad, I didn't nag enough. I forgot your background and assumed that you've used external trigger. Digital signals are not defined by repetition, that's for next level. There are no practical settling time either, every moment counts. For low frequency things like this these moments are transitions, so change of level either up or down. There is of course a transition delay, but that's it, after that the same thing can't happen again before that same transition happens. So it's either rising edge or falling edge, usually only one, but 68k CPU can use both. CPU R/_W pin defines writing when it goes low, so falling edge. Read doesn't happen when level goes up, it's defined elsewhere. Those read and write moments are part of cycles, there are also many other cycles. Before those actual read and write operations have meaning there must be an object. That object must also have time to adapt, transition delay again. Same with all parts around that happening, like buses. Cycle includes all of those moments, one cycle lasts many clock pulses. Generally cycle must end before next can start. Since R/_W pin defines writing it can also define its end by going up. That is a normal procedure, down is starting and up is ending for generally everything of falling edge things. Inside a cycle are different periods. It is said that certain time period the thing is valid, like data in write cycle. So at some point when R/_W pin is down the data must be present, address also. Since everything are based on clock pulses and everything can't happen at once there is a propagation delay. That's sort of a settling time, but not for a signal, it's settling of different parts of a circuit and can last more than one clock pulse. For that datasheets have cycle timing pictures. When chip is accessed it is first selected. There can be many chips selected at once, but then occupied bus must support that. Usually address bus is for many and data bus for one, in our case I/O address bus is also for one. Chip can also be valid only when it is selected, so when _CS pin is down, underline means active low. |
| m k:
--- Quote from: stfjohn on September 26, 2024, 03:13:14 pm ---the scan varies at least 4 times --- End quote --- Our POD 00 to 05 are 6 address pins of 23, so there is an assumption that those 6 can indicate enough. Your latest set of pictures have POD 06 going down, that moment is only moment when that chip is selected. So address pins of that period are for that POD 06 chip. All other addresses, before and after, are for something else. Bright side is that those pictures have also many other chip select lines. So if none goes down the address is also for none. Down side is that 6 address pins of 23 can't tell much without that chip select line. But we have other pictures and there is a pattern. My guess is that those wide up, short down and wide up again sets are real, and if CPU R/_W pin is connected it is just like it was earlier when it was connected. POD 06 5E10xx 63484 5 _CS CRTC POD 07 ---- 71054 31 _CS U52 timer POD 08 ---- 71054 31 _CS U67 timer POD 09 ---- 71054 31 _CS U86 timer POD 10 *** 68450 17 _CS DMAC POD 11 *** 62421 2 _CS0 RTC POD 12 *** 62421 15 _CS1 RTC POD 13 ---- 32081 21 _SPC FPU POD 14 ---- 8279 22 _CS KBC POD 15 *** 9914 3 _CE GPIB Dash line pictures are aborted, so no trigger. Asterisk line means that somewhere in the data that _CS POD pin goes down and there is an address for that chip. Chip select of floppy controller is not connected. Same with stuff like MODESET. something else in a picture, none of above POD 09 5F1Cxx POD 11 5E30xx * POD 12 5E2Cxx POD 13 5E30xx * something else in earlier set of pictures, none of above POD 09 5E38xx * POD 10 5F0Cxx POD 11 5E20xx POD 12 5E28xx POD 13 5E00xx POD 14 5E2Cxx POD 15 5F04xx something else in even earlier pictures R/_W signal present and writing 5F1Cxx 5F08xx 5F34xx * different timing |
| stfjohn:
I redid everything using the ext output trigger of the HP 1651A and with single acquisition. However, each time, I get different scans... I don't know! |
| m k:
Change POD 06, connect it to CPU R/_W pin 9. Then do POD 07 to 15 once more. Maybe those differently timed signals are also addresses. If new POD 06 goes down under them we know they are. You can also scroll left and right to see different settings. Then put analyzer a side for a moment, leave test pins as they are, if there is no harm, and pull motherboard out, or not if you're already familiar enough for measuring the under side. No need to get stuck with the analyzer, but don't give it away if you can keep it. Then start finding motherboard traces, that's at least more exact science. Concentrate to high addresses of CPU first, A22 down to A20, pins 51, 50 and 48. Check if you can find a connection, reply #74 has some chip stuff. PAL chip pins 1 to 9 and 11 are inputs, CPU addresses can be connected there. 3to8 line 74138 pins 1, 2 and 3 are inputs, that's other promising target for CPU addresses. Next level goes so that previous chip's output is next chip's output enable, for 74138 that's pins 4, 5 and 6. If you find a connection between 2 logic chips you can start finding lower CPU addresses from the receiving chip. Since some I/O area addresses are not used there can be gaps all the way, that would be a partial addressing where many addresses mean the same thing and nothing unusual. There can be also a single gate coding those unused address pins, since 74138 has 3 enable pins that's even a probable design, but 1 must come from the higher level 74138. If finding traces start irritating update those unknown chips from end of reply #83. It's likely that one logic chip is not in order, so you possibly need to find it anyway. I'll check if I can see the light in analyzer manual. Seems that the current setup is 16 timing and 16 state channels. We can possibly see more if we use 32 state channels. With luck we can then forward the program step by step and finally see exactly what and where is the problem. Since many I/O chips are 8 bits wide we can drop half of CPU data bus off and use freed pins as _CS pins and then use them as stepping stones for software hops. Pictured addresses, not for triggering _CS pins. POD 06 5F04xx POD 07 5F0Cxx POD 08 5E14xx * POD 09 5E10xx * no CRTC _CS POD 10 5E2Cxx POD 11 5F30xx POD 12 POD 13 5E38xx * POD 14 5E34xx * POD 15 5E28xx * * different timing E, Very early picture 3 and POD 11 of reply #84 have similar happenings. Maybe 5E30xx has something to do with the problem. |
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