@robot.golem Noting of course that there are multiple revisions, my notes say
PCB is "Rev.15". All chip identifiers obliterated, TTL outputs via 330R, TTL inputs unidentified.
Don't know whether TTL Rx monitors the CH341 signal or can be used to drive the Big Chip.
Photo of a Rev.10 PCB at
would suggest that the Rx signals are distinct.
I presume that the (Lattice?) FPGA implements a simple CPU for command parsing, although it
would be simple enough for this to have been handed off to the STM32 on the back of the display board.
...so I think it's probably fairly important to get the right board version, and there's still the possibility of gross incompatibilities in the FPGA.
@SpecialK I ended up getting a JDS6600 since I needed something in a bit of a rush and somebody was quoting a good price (subject to international delivery time, and the seller looking as though they had a one-off that they didn't know anything about). So far it's doing what I needed.
I must say that I'm rather taken by the additive encoding used to construct arbitrary waveforms. At some point I'll redo the software for Linux (which will probably also run on Windows, but that's of little interest to me) and will consider enhancing that with a full set of APL-style array operations... not that I'd expect anybody else to notice or to recognise them :-)
MarkMLl