We would need a 256k x 16 FRAM, probably 4 level translator chips, there are no 256k 5V chips, a 3.3V regulator and couple more gates.
Don't we need 2 separate 128k x 16 bit FRAM/MRAM/NVSRAM for the 2 separate (probably interlaced) CE lines?
I'm not quite sure if you can remap the 2 CE lines to the double address space easily.
You may be right and that is becase of byte writing. The way I read the schematic is this:
1. There are two 16 bit memory blocks. LUSERRAM0 (U1, U2) and LUSERRAM1 (U6, U7). These cannot be active simultaneously because there would be conflict.
If this is correct we can use LUSERRAM1 as an address input.
2. There's only one output enable LOE that goes to all four chips so no worries there.
3. Writing can happen on the upper or lower byte or both, controlled by LLW and LUW and that's a problem.
Even more, depending on the processor speed, I don't think 14.7423MHz is that fast though, this FRAM may be too slow. The SRAM read and write cycle time is 70nS, the FRAM is 110nS.
We'd have to measure the memory access timing to see if the FRAM is an option. If it is, LCSC has FM22L16 at ~11USD, not too bad, we need 2 per. Unless the access is very slow and we can make UB, LB and WE from LLW and LUW, in which case one chip is enough.
