Hi Miti,
I've resolved the SW issues with the Nucleo board, and have the FRAM and a break-out board in-house. I need to assemble it and write the test SW. Still a bit more to do. I have some other activities getting in the way at the moment, and I apologize for the delay.
I know you want to get your board done. You have a working solution, and I won't be insulted if you decide to proceed.
The general plan is to be able to read/write the FRAM under SW control via GPIO bit-bang for initialization and read-back with known data, and then use the FMC (memory controller) peripheral to stream control pin changes clocked at 200MHz to the FRAM control inputs. The data I/O pins from the FMC will drive the control inputs on the FRAM, so any arbitrary sequence of control ordering can be created, and at any timing, by crafting the data out pattern. After streaming some high-speed test writes using this method, all locations will be read back at slower speed and checked for valid writes in the expected locations, and invalid data or writes to a wrong location.
Previously, I thought I could achieve 2.5ns granularity, but there is a "CLK+1" in the FMC timing specifications, so I will get 5ns granularity with a 400MHz processor clock (that's the max). I verified the 5ns FMC timing with a scope on the Nucleo board, so I am confident this approach will work. 5ns should be sufficient for our purposes, but if something is really close, there's always physical coax delays that can be introduced.
I kind-a wish I hadn't sold my 300MHz 24-channel Agilent 16720A pattern generator several years ago. I never used it, but it would have been perfect for this.
I will post updates.