Electronics > Repair
Has anyone replaced HP8591(E) SRAM by FRAM?
MarkL:
--- Quote from: Miti on January 07, 2025, 03:00:42 pm ---I have a question about the bidirectional level translators such as TXB0108. I see it has an OE pin for the LV side. Can I connect it to Vcc or does it have to be controlled? What happens with the 5V side if I tristate the memory side and the LV pins are left floating? I’m asking because the enable time Ten is 1uS and it is a killer. :palm:
Cheers,
Miti
--- End quote ---
You might want to control OE if you have a partial power-down application (meaning power-down on the VCCB side). Otherwise it does not need to be controlled, which is the situation here. You should tie it to VCCA since it is referenced to VCCA.
However, you should read the section about pullups in the datasheet: 7.3.5 Pullup or Pulldown Resistors on I/O Lines, and 8.2.2 Detailed Design Procedure. The TXB0108 presents weak pullups and pulldowns to both sides of the translation so that either side can force the bus to the desired state. If there's other pullups or pulldowns it can interfere with this operation. The 859xE series has a 10k resistor array (U11) plus R19 (for qty 16) to provide pullups on the data bus (see block E on the processor schematic). These pullups are going to interfere with the TXB0108.
Also, the data bus goes a lot of places, so 7.3.3 Output Load Considerations, which talks about capacitive load, could also be a concern.
I would recommend to design with standard bus drivers and create the logic to control direction. These automatic bidirectional drivers sound like a dream come true, but I've always found a reason not to use them in my designs.
Miti:
Thanks Mark, yes I saw the 4K resistors series with the drivers but I missed the 10K pull-ups. Would 74LVC4245 be a good choice? And what would be the direction and the OE logic?
I’m thinking LUSERRAM0 and LUSERRAM1 would control buffers OE and module OE would control direction. When FRAM OE is high, direction is CPU to memory.
Cheers,
Miti
Edit: Or maybe 74ALVC164245 but it may be harder to layout.
MarkL:
The 74LVC4245 looks like a good choice.
The direction and OE control I think would have to be some combination of LUSERRAMx, LLW, and LOE.
Take a look at the existing memory HM628128 datasheet. The /OE input going low does not always mean "from memory", specifically during Write Cycle Mode 2 (truth table below). I don't know which mode HP is using and there is a PAL (U114) involved in the memory signal controls, so the behavior can't be determined by the schematic alone. To be safe you should probably emulate all combinations of the HM628128, but you could also scope the memory control lines and figure out exactly what they're doing, which may allow you to simplify the new control logic (for example, they only use Write Cycle Mode 1).
I think 74ALVC164245 would work too. The layout doesn't look too bad. At least all the A's and B's are on opposite sides, so it's still flow-thru.
Miti:
Ok, I've checked. OE is always high when either LLW or LUW goes low. I'll assume mode 1. Do you have any reason to believe it uses mixed modes?
MarkL:
I wouldn't expect them to mix modes. As long as you didn't catch it doing Mode 2 you should be ok. I think they would probably only use Mode 2 if they decided not to control /OE at all.
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