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What do you think about my timing diagram in reply #52?
The timing looks like it would work for the FRAM, but I'm not sure you need to go through all the trouble for extra delays on /LB, /UB, and /WE. I also looked the schematic. Note that for a 16-bit read, both /UB and /LB need to be pulled low along with /OE (and qualified by LUSERRAMx).
If you read the text of how the various signals work, the FRAM is very forgiving in the order in which things happen. As I mentioned before, the write occurs on the rising edge of /WE or /CE. /LB and /UB have to be setup 25ns before that (tBLC). /LB and /UB can coincide with /WE (or /CE) since it's the rising edge that matters and the /LB and /UB hold time is 0ns (tBH). Said another way, /LB and /UB must not change 25ns before either /WE or /CE goes high.
The address has to be stable 0ns (tAS) before /CE goes low, but if they change afterwards the new address is latched and it operates in a /CE low cycle.
Maybe try this: You have the following control signals coming into the board: LUSERRAM0, LUSERRAM1, LOE, LLW LUW. The FRAM inputs are /CE, /UB, /LB, /WE, /OE. Write the logic equations for the FRAM inputs in terms of the incoming signals. Or sometimes it's clearer to write out all the combinations in a truth table, in this case 32 rows, with inputs on the left and the desired outputs on the right. Then it might be easier to see if any gate delays, one-shots, or any other signal massaging is necessary.
EDIT: And another FRAM input to include, if you do equations or a table, is A17.