How dows this PLL work and what could be wrong? Decoding of PLL config?

[petemate]

Hi guys, in my other topic on repairing a TTI TGA12101, I mentioned that the FPGA seems dead when communicating with its RAM. I did a little more digging and noticed that a PLL had an LED indicating that it was not locked. Looking at a clock from the PLL to the FPGA, I see a frequency of 21.7Mhz. The frequency is supposed to be either 25-50MHz or a constant 50Mhz(This depends on the operating mode of the arbitrary waveform generator). The manual specifically mentions that it is possible for the FPGA to become non-functional if this clock signal is interrupted or "incorrect". I am wondering if that is the case here, since 21.7MHz is well below 25Mhz, which should be the minimum. Maybe the FPGA checks the frequency and cant proceed if its outside specs.. The FPGA does have a "LOCK" led that doesn't turn on and I don't see how it should know to be locked, since there isn't any communication from the PLL back to the FPGA(except for the frequency, that is).

Here is the PLL circuit. The 21.7MHz is measured at PJ12B-A:



The problem is, the PLL is enclosed in a tin can that I really can't get to. I can only get to the connectors PJ98 and PJ12B, located around the edges of the tin can. I measure the VCO test-pin to 11.589V. I don't know if this value is what its supposed to be, but I see the value shoot pretty much straight up at turn-on. I am not completely sure how the VCO voltage is affecting these varicap diodes, but if I understand correctly, then more voltage means less capacitance and hence higher frequency. If the voltage is as high as it is and the PLL frequency still hasn't reached 25-50MHz, i'd argue something is wrong. What are your thoughts on this? It also puzzles me that the voltage is as large as it is, since D201B and D202B should clamp the actual voltage at the varicaps to ~1.4V.

A voltage of 11.6-1.4 = 10.2V across R237B would also dissipate aruond 100mW in it. Its an 0805, so it could be fried, which explains the large control voltage and the missing lock.

In order to verify that the PLL is indeed trying to output 25-50MHz, I decided to take a look at the configuration data sent to IC212B. By knowing the input frequency(REFCLK, sent to OSCIN is a dead-on 10MHz) and knowing the various divisions performed by the PLL, one should be able to calculate what frequency should be produced by the LC tank..

I had a look at DIN, ~ENB and CLK with my Saleae:



It appears that there is first a pulse chain of 32 clock cycles, then a pulse chain of 40 clock cycles. This makes no sense according to the datasheet. The PLL loads its various registers according to the number of clock cycles received while ~ENB is low. But I can't get those clock cycles to match up with the description in the datasheet. Can anyone help me out with decoding the pulses and tell me what they say?

Link to datasheet: http://doc.chipfind.ru/pdf/motorola/mc145170d.pdf
Link to updated datasheet: https://www.nxp.com/docs/en/data-sheet/MC145170-2.pdf

Table 1(table 7 in the updated datasheet) is the important part. It shows how a length of 8 clocks writes to the C register, 16 clocks writes to the N register and 15/24 clocks writes to the R register. But this doesn't add up with the bit pattern I read out. In the updated datasheet, there is some mentioning of bit patterns longer than 32 clock cycles, but that still doesn't explain the 32 clock cycles. Can anyone point out what I missed?

Next step is taking off the tin shield, but unfortunately it is most likely a destructive process that I'd like to refrain from if possible..

Thanks for your input, guys!