I was looking through the manual and it looks like you can use another signature analyzer to check the signature analyzer.
It looks like a bunch of logic chips so there's probably a bad one somewhere. You should be able to track it down with a scope and/or logic probe while it's in test mode.
I have the HP 5005B Signature Analyzer / DMM, it has a self test function for basic signature function tests.
I looked into the O&S-Manual of the 5004A.
Ch 3-14 (page 19) describes same (including the procedure in Figure 3-2 below)
Did you walked through this procedure?
What's you results - this will give the first hints for troubleshooting.
BR
PeLuLe
PS:
You may have a different version (the Keysight one is just useable for manual changes).
For your convinience I have uploaded my HQ PDF of the Q&S manual under below link.
I will delete the file in 7 days, as I need the storage for a joined project.
https://www.dropbox.com/s/xspsu9umbz889b9/HP%205004A%20Signature%20Analyser%20-%20Operating%20%26%20Service%20Manual%201977-03%20%2805004-90001%20HQ%29.pdf?dl=0 (https://www.dropbox.com/s/xspsu9umbz889b9/HP%205004A%20Signature%20Analyser%20-%20Operating%20%26%20Service%20Manual%201977-03%20%2805004-90001%20HQ%29.pdf?dl=0)
Please understand I am not an EE so I apologize for the rudimentary questions.If you have no electronic experiance, you are in trouble. In that case I would try to find some help in your area. :--
Test points 4 shows an incorrect signature (display's A446 when it should be HH46) and test points 7, 8 and 9 are incorrect as well in Normal and Service mode. All the others show correct. The 5v test point, I have 4.82v.The 5V (4.82V) is ok in my view 3.6% deviation is will in the by TTL tolerance.
Am I to assume it means check...U25, U26 and U27 are 8 bit counter (I assume binary types).
In Germany self-repair support shops are becoming more and more popular. There you will find tools, knowledge and help (I am supporter of such a group here in my area).
The only abnormal thing I am seeing is pin 11 on U25 is stuck low.I recommend some more measurements bevor soldering.
U25 is a counter: pin 2/3 are enable inputs (AND), pin 5 seems to be the reset (active high), pin 1 is the clock input, pin 11/8/9 are the counter outputs.
If pin 11 (1st counter stage output) stays low, this may also caused by "no counting" or "reset":
- no clock at pin 5
- a low state at pin 2/3, a short low pulses may have the same effect if tming fits
- a high state at pin 5 (f.e. self test switch in Position ON).
Do you have a logic analyzer or a 4ch scope available?
In that case I recommend to measure at same time pin 1/2/5/11 to check if the condition prevents counting/change of the ouput
BR
PeLuLe
Then first take some other measuremens at same time singnals at U25(
A 4ch-scope is much better than logic analyzer, as you are able to see quality of the signals also.
I am not sure what does mean "pins 1 and 14 of U25 were just flip flopping high and low".
But to check of U28 (clock IC) should be easy. Output Pin 3 must be a stable frequency (~50% duty cycle).
I expect it is OK and you need more measurements to dig to the error.
For all measurements you need to look to U10/Pin 6 (reset) at te same time to be sure it stays (?) at LOW.
It is the signal NOT(U28/QD & U25/QD) building a feedback loop to generate the test signal.
So it will not stay at LOW forever...
U25, U26 and U27 are 74LS93 (4-bit asynch binary counter, HP parts 1820-1478).
Pin 2 and 3 are &-wired reset inputs, both need to be HIGH, to get an reset - here they are connected and LOW.
Pin 14 is clock input CKA of first counter stage A, Pin 1 (CKB) is clock input of the remaining counter stages (B-D).
Typically (as also here) the first stage output QA (pin 12) is connect to CKB to buld a complete 4-bit counter.
Conclusion: U25/Pin 1 must have exact the half of the clock speed of U25/Pin 14 (binary devider).
Is that the case?
If NOT: U25 may have a defect and should be replaced.
If YES:
U25/Pin 14 must be same signal as U27/Pin 11 (U27/QD).
U27/Pin 11 (U27/QD) must exact the half speed of clock of U27/Pin 8 (U27/QC).
In that way should be able to check/follow the signals back to U28 (clock IC)
BR
PeLuLe
But to check of U28 (clock IC) should be easy. Output Pin 3 must be a stable frequency (~50% duty cycle).
I expect it is OK and you need more measurements to dig to the error.
For all measurements you need to look to U10/Pin 6 (reset) at te same time to be sure it stays (?) at LOW.
It is the signal NOT(U28/QD & U25/QD) building a feedback loop to generate the test signal.
So it will not stay at LOW forever...
Conclusion: U25/Pin 1 must have exact the half of the clock speed of U25/Pin 14 (binary devider).
Is that the case?
The video does not answer the questions unfortunately.
It just show one signal at the time, so I am not able to compare the signal timing and sychronization. What can be seen: you have triggered the first signal to a stable picture, for the other not. They are slow (as expected, see below) and you keep the horizontal setting time/div at the scope unchanged.
You may want to connect at least two signal (CH1 & CH2) at the same time, set time/div to the slowest signal. Than you are able to detect, if the 2nd signal is excatly the half speed of the 1st - as it must at a binary counter stage.
Each stage is a divider by 2, so the 4 bit binary counter is a diver by 16.
Signals should look like:
CH1: __HHHH____HHHH____HHHH____HHH
CH2: __HHHHHHHH________HHHHHHHH___
Clock of U28 (clock IC) is ~600 Hz (0.6 KHz), so:
U26(12) ~300 Hz - U26(11) ~38Hz - U27(12) ~19Hz - U27(11) ~2.4Hz - U25(12) ~1.2Hz - U25(11) ~0.15Hz
Means the loop runs ~7 seconds. Than it should reset the counters and restart at the next low output of U25(11).
Lets first check, what kind of test equipment you have available beside the 4ch scope.
Do you have
- a logic analyzer (>= 8 channels, >= 10 MHz)?
- a frequency counter (>= 10 MHz)?
How is your knowledge regarding signature analyzers principle? If you not understand the principle of signature analysis, you will stumble around like a blind in the fog.I have attached an very good article from HP Journal, when HP introduced the 5004A. This may help to get a better understanding.
I have attached the link to a very good article from HP Journal, when HP introduced the 5004A. This may help to get a better understanding (file too big to attache):
http://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1977-05.pdf%2Fwww.hpl.hp.com%2Fhpjournal%2Fpdfs%2FIssuePDFs%2F1977-05.pdf&usg=AFQjCNGFSQWK8RkSBEG2EfBv7AtRSyW5aA&bvm=bv.114195076,d.bGs (http://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1977-05.pdf%2Fwww.hpl.hp.com%2Fhpjournal%2Fpdfs%2FIssuePDFs%2F1977-05.pdf&usg=AFQjCNGFSQWK8RkSBEG2EfBv7AtRSyW5aA&bvm=bv.114195076,d.bGs)