About the 4 bands
100k-123.5M (heterodyned)
123.5M-247M (divide by 4)
247M-494M (divide by 2)
494M-990M (divide by 1)
divide 50 Mhz reference , changing frequency from front panel increasing or decreasing 1 Mhz steps
the output change only every 50Mhz in the first band , 12.5Mhz in the second , 25 in the 3rd and 50 in the last high band
look like the divisors is working but something else is wrong , tracing with scope found weird signal here at MC10138L chip divisor
scheme section:
pin 15:
pin 14:
pin 4 and 12: