HP8753C won't phase lock below 16MHz with A9 CC jumper in 'NORM'

[Michael-VK2BEA]

I'm trying to resuscitate an HP8753C.
I replaced the YTO, which was bad and was able to do the 'Source Pretune Correction Constants' adjustments procedure.
This is done with the A9 jumper in the 'ALTER' (right most) position. After adjustment the jumper is returned to the 'NORM' (left most) position.
When I do this I do not get phase lock below 16 MHz (low band).
The High/Low Band Transition Adjustment shows normal (right hand trace ~150mv higher than left).
 Do anyone have a clue as to what might be wrong?  Why would the jumper position effect the performance of the PLL?
First attachment ... with A9 jumper in 'NORM' position
Second attachment ... with A9 jumper in 'ALTER' position

[Bud]

Ask the mods to move this topic to RF Microwave or Test Equipment subforums. Joel Dunsmore, the designer of 8753 frequents those subforums. Or you could PM him and ask to take a look at your post in this subforum.

[Michael-VK2BEA]

Thanks for the suggestion!

[Joel_Dunsmore]

You might try checking the frequency of the cavity oscillator. It should be at about 3.8 GHz +- 5 MHz.  There's a hex-head screw on the top that adjusts the freq; if it gets too far off frequency the source might not be able to look.  There might be a YIG pretune correction as well that you might need to do before doing the source phase lock correction (although, I forget if that's only on the 8720 and 8722).  You might need an external SA or freq counter for YIG pretune.

Above 16 MHz we use a sampler to down converter so even if the YIG and cavity (they are mixed together to produce the source signal) are far off frequency, they will land somewhere near a sampling comb-tooth and get converter to the IF frequency so we can lock to it.  In low-band (below 16 MHz) the sampler (i.e. frequency converter) is actually bypassed and the signal is fed directly to the IF; so if the YIG or cavity is off by more than 16 MHz, the lock will fail. 

There is a cavity oscillator frequency adjustment test (maybe in the 30's) that might help if run, but it can only account for a most amount of drift. The orginal design was such that we expected we would need to re-run the calibration every 3-5 years; it's probably due.

[Michael-VK2BEA]

Hi Joel,
  Thanks for responding and for your suggestions.
As is happens about two hours after I sent the note, the mail arrived with some blank ROMs to update the firmware. I did this and the problem went away.
This unit has the newer PLL board but it's came with version 4.01. I upgraded to 4.13.
I saw the software notes warning not to use newer software on the old PLL board but perhaps the reverse is true, giving me this unusual problem.

I have absolutely no idea as to the history is of this unit I got on eBay. It was sold as fully working but so far (apart from this issue) I've found the YIG was dead, the display is bad (there is a horrible purity issue) and the S/N is bad (the noise floor is only -80dB on both channels).

I'll replace the display but do you have any pointers on what might be up with the S/N that would effect both channels? (edit: never mind I was measuring the noise incorrectly! The RX 3kHz / 10 Hz noise is actually good. I forgot to account for the insertion loss of the test set )
regards,
  Michael

[Maurizio1957]

Hi Michael,
 where do you find the YIG oscillator? I have a 8753C with a dead  oscillator!
73, Maurizio IU5BEC