Electronics > Repair
Keithley 197 - jitter/jumping last 2 digits
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Kleinstein:
CR102/CR104 are used for input clamping. The 1N4148/ 4149 are rather high leakage (comes with the high speed) - so the BAS45 would definitely be some improvement.
One may still get away with the 1N4148, as the leakage current can compensate from both sides. So if the zero is good enough one could as well keep them. U104 pin 6 should show the resulting DC offset.  Chances are more of the offset is from U104 compared to the diode leakage.
corehbola:
Hello TRobbins,
It's been a while since my last update on this issue on my Keithley 197, which by all means, looks very similar to yours.
I went through some house renovations which made my dungeon (sorry, my lab) unusable for more than a year.
Since a couple of months ago when I could start using my lab again, I think I can finally share some "discoveries".

1. Having ever wondered why, when grounded through a 10M resistor the readings would jump between some 0.5mV and every once in a while 1.5mV, I did an extensive troubleshooting and eventually found out that this is somewhat of a quirk of this meter's design.
It has to do with the Input bootstrap buffer, that is used to bias the Multiplexer FETs, and the way how the meter cycles through the different MUX inputs.
As the meter switches over from reading the Vref (2V, through Q113) and reading the Input (through Q111), right after the transition from having Q113 activated to having Q111 activated, the voltage appearing at the bootstrap amplifier output is still the 2V of the previous input.
When comparator that was enabling Q113 pulls its gate to -9V to cut it, and the comparator that will enable Q111 "opens" its O.C. output...
At that very moment, the voltage that is still present at the output of the bootstrap buffer (U101B, pin 1) is 2V, and since it's greater than 0.7V, it directly bias the gate to source junction of Q111, and current flows from the bootstrap buffer, through Q111 bias resistors, through Q111 gate-source junction (now innapropriately forwarded biased) out to the input stage of the meter, through R106, and ultimately ends up charging up C109.
Since the input is tied to a high impedance (10M), even though the bootstrap buffer remains at 2V for very little time, it's a low impedance source that charges the input capacitor by a small amount... and this charge lingers on enough to be sampled by the A/D converter (even though Keithley claims the A to D conversion happens after a software controlled delay that is implemented exactly to overcome the glitches that are created by the FET MUX switching).
But the FETs gates being forward biased after every transition from an input with a higher voltage (i.e. Q113 with 2V) to an input presenting a low voltage (i.e. Q111 with any voltage lower than 2V - 0.7V) is not the only place where that happens...
It also happens due to the clamping transistors Q114, that also "discharges" the 2V present at the output of the bootstrap buffer, into the FET MUX's output.

Alright, that's one part of my findings, but still... Why sometimes a lower value (around 0.5mV) and why sometimes a larger value (1.2 to 1.8mV in my case)?

2. That's when I scoped the FET MUX's activation signals (coming from the PIA) and realized that Keithley somewhat "cheated" in their claim of 3 readings per second!
It indeed reads the voltage input (Q111) 3 times per second, and it indeed reads the other inputs to keep proper track of Input Buffer Offset cancellation and gain drift, but those other inputs are not read 3 times per second... they're rather read 1 (or sometimes 2) times per second... as follows:
* At 200mV and at 2V scales (where there's no input attenuation from the input voltage divider) every second it switches the FET MUX 6 times:
a. it reads the 2V reference (Q113) once.
b. it reads the input voltage (Q111) once.
c. it reads the "zero" voltage (Q112) once.
d. it reads the input voltage (Q111) a second time.
e. it reads the input "zero" (Q112) a second time.
f. it reads the input voltage (Q111) a third time.

* At 20V, 200V and 1000V scales, it does more or less the same, but at step e., instead of reading the 0V input a second time, it reads the lo-side of the range attenuator voltage (through the range attenuator MUX comprised of Q104, Q107 and Q108) to be able to read the voltage drop on the range switch FETs (Q105, Q106 and Q109) and be able to compensate for the error introduced by them.

For each one of the six times above, it performs a complete A to D conversion so, it's not like in regular, non-microprocessed meters, that the reading of the zero, and the reading of the Vref is part of every A to D conversion...
The part of the A/D conversion that is related to "zeroeing" the A/D input is performed further down in the signal chain by U105B and Q119, and the part of the A/D conversion that usually requires the reference voltage, is performed, partly by the summation resistors R117A, R117B and R117C, and partly by the single slope current source R129, that is switched in to +5V by U105C.
In the 197 instead, it reads the 2V reference (Q113) 1 time per second, and it uses the value read during this one time, for the subsequent 3 voltage readings to compensate for any change of gain of the input stage.
And finally it also reads the 0V input (Q112) just once per second as well (twice for the 200mV and 2V ranges), to ocmpensate for any offset (and offeset drift) of the input stage.

3. Having said that, to fight (and possibly rule it out) that "design quirk" of the input FET MUX where the gates are momentarily forwarded biased, I designed an entire new analog switching MUX, using modern analog switch ICs, and replaced all the FETs in the input MUX by a MAX329 analog switch, all the FETs in the range attenuator switches by an DG412 analog switch (for its low RDSon), and all the FETs that samples the range switch voltage drops, by a MAX327.
I could have made the input MUX with the MAX327 as well, but I decided to use the MAX329 because, being a 4 to 1 analog switch, it has internal "brake-before-make" delay, which would make it impossible for any charge injection due to any glitches in the transitions from one input to another...
Sure enough though, to drive the selection binary encoded inputs of the MAX329, I had to convert the 4 FET control inputs (coming from the PIA) into 2 bit encoded signals (4 combinations), using a CD4532 priority encoder.
It was a challenging prototype, because it needed to fit exactly in the area of the PCB where all the FETs are, but I managed to make it and it's working exactly as intended.

Still, even though I ruled out completely that "charge injection" that could be possibly coming from the FETs' gates being forwarded biased... (there's no room for that to occur anymore because the analog switch ICs use CMOS transistors and not FETs)...
The same weird behavior of a reading around 1.2mV to 1.8mV every once in a while, still happens...

So, there are more misteries yet to find out.

Kleinstein:
Interesting to see that the meter does more than the simple AZ cycle with 3 readings. To a certan degree it makes sense to use a zero or reference reading for a longer time. However this can interfere with the suppression of 1/f noise and lead to thus more than normal LF noise. A similar effect is a candidate for the extra LF noise seen in the K2002, DMM7510 and a few more Keithley meters.
I had no so much expected the more complex cycle already in the old meters.

Changing the input switching is quite some effort for such an old meter. CMOS switches can make things a little easier, bit they can also have some switching spikes / charge injection.
With a rather high impedance source it is normal that the recovery takes longer and the waiting time by the DMM may not be sufficient. With more normal signal sources this may not be an issue anymore.
It is still a bit odd to get outlyers only relatively rarely - there would be special readings in the cycle (e.g. temperature) or maybe coincidence with data transfmissions. Another nasty source for interference are mobile phones - they sometimes send relatively strong pulses.  Wlan may also occasionally get more active, if the are collosions or a new participant stirring up the configuration.
corehbola:
Thanks Kleintein for the heads up.

Indeed, without absolute knowledge of what the firmware is doing, it's a pain to troubleshoot the A/D, because nothing can be taken for granted (since the uP is actually entitled to do whatever the programmer felt like doing).
There's just so much that we can deduce by just looking at the pure sequential logic (the few gates, counters and flip-flops that are used in the charge-balance section of the A/D), that works on its own independently from the uP.
And the Theory of Operation described in the manual is very, very superficial.

Since the signals repeat so slowly, to me at least who have an analog oscilloscope with only three channels (even though with storage CRT), it was hard to catch the spikes during the MUX transitions, but they're there! They raise all the way up to 1.5 ish volts, and the big part of them last for some 200us.
But the evil is in the lingering... as the discharge is exponential, after the greater part of the spike went away, the reminiscent charge can take quite long to dissipate and it's impossible to see it well in the oscilloscope because it's Hi-Z and 60Hz pick-up gets in the way of a cleaner reading (and adding a capacitor to filter out the signal is not an option).
And I was only able to reach any conclusion because in my scope (a Tek 7623A), I have a 7A13 (differential comparator), which allowed me to increase the gain all the way up to 1mV/div and use the infinity impedance input (whch is quite leaky in comparison to the 197's input btw).

But further down the rabbit hole, I`m finally coming to a conclusion about what was annoying me the most, which is the quite high noise of 2 digits (+ or = 40ish counts), even shorting the inputs.
I knew the charge injection from the MUX was a "bitch", but I also knew it could not be the cause for that with shorted inputs.
And as this +-40 counts are irrespective of range, I knew it could only be from the A/D itself, so I went down that road and started investigating the A/D operation.
I was looking at the output of the integrator and finding it very weird that I could never see it goes through the "Single Slope" stage of the conversion.
I could see it doing the multiple charge-balance up/down ramps, but it would never go to zero volts... instead it was going - every so often - to saturation of the A/D integrator op-amp (all the way to +V).
At first I wasn't sure if that was some artifact from the way how the uP controls the process... but as I dug a little bit more into the A/D workings, I can now tell for sure there's something wrong with the A/D.
It seems it's not performing (at all) the last stage of "Single Slope" conversion...It's obtaining whatever readings it's getting with only the result of the first stage of the conversion (i.e. the "charge-balance" stage).
I never thought it would be even possible to have such a "gross" malfunction and the meter still be able to operate... but that, I think, it's thanks to the "software calibration" feature and the fact the calibration constants can compensate for a very wrong reading.

And no, I never "reset" the calibration constants because I was in the hopes I could still get away with having to calibrate the meter again. |O

Right now I have unsoldered all the analog part of the A/D circuitry because I wanted to be sure there was nothing hiding under the components (maybe some contamination, or solder flux, etc...), and also be able to confirm out-of-circuit, if all the components are healthy.
But as soon as I put everytihng back again, I`m sure I`ll be able to monitor the relevant control signals and understand why the A/D is not performing the last "Single Slope" conversion stage.

I`ll keep you all posted. I think I`m very close to solve this problem (which I think is exactly the same as what @Trobbins have).
Kleinstein:
There is no really clean separation between the analog and digital part. The flipflop U117 is used also as an analog switch to control the reference signal from the +5 V_A.
The ADC seems to need a rather stable supply for the +5VA = reference for the ADC, +5 V_D and the -6.4 V (used for offset to the ADC input and thus ideally derived from the +5V_A and not a separate zener reference  :-//). With only 5.5 digits they may get away with a lot of things that are not ideal.

If the slow rundown is not working at all this could be an issue with U105 / R129 , but also the logic part controling the rundown. Ideally I would have expected an error message as the µC should detect that it never reaches zero. A first point would be to check the control signal (U105 pin11 = comparator output). U105 is worth checking as it get signals from a different supply than it's supply and the old CMOS chips were a bit susceptible to latchup.

To get all the way to positive saturation for the integrator could be an issue with excessive leakage at the integrator input  (e.g. gate leakage of Q120). So the 1 M resistor to 5 V may not be strong enough to overcome this. For a crude test one could try some extra resistance in parallel to give it more power.
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