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mosfet H-bridge motor driver repair (unobvious problem in circuit design).
Posted by Ivan7enych on 21 Oct, 2016 11:10 -
Hello, let me share a little experience in one repair.
I was asked to replace burned mosfets in meade telescope mount
http://www.meade.com/products/telescopes/etx.html
After replace I've found that even new mosfets are getting very hot (98c) in a seconds.
It took me some time to draw part of sceme.
They use mosfet H-bridge to rotate DC motor in one or another direction and optical encoder on its axis as a feedback to reculate speed.
I draw part of this H-bridge, see picture.
IN1, IN2 - outputs from microcontroller.
IN1 = 0, (Q3 is closed, gate Q2 = 12v, and Q2 is closed)
IN2 = PWM signal, switching on and off Q1.
Q2 is getting very hot, why??? It should be closed!
I look at Q2 gate with oscilloscope and see big spikes opening it for some time.
I see at Q3 base - everything is clear.
After some thoughts I guessed that Q2 have some capacitive coupling with it's source pin
and when Q1 opens, Q2 source jumps from +12 to 0, and that jump goes via capacitive divider (drain-gate | source-gate) to the gate, opening it and making short circuit through Q1 and Q2.
How to fix this? I can't make R2 lower, it will burn when Q3 opens. The only way I see is to add extra capacitance to gait-drain, to make this capacitance at least 10 times larger than internal source-gate capacitor. There's no PWM here, so I don't care about larger switching time.
I multiply by 10 source-gate capacitor (300pF) and add 3nF to gait-drain.
As a result I see spike on gate Q2 becomes much smaller and doesn't open Q2. (yellow trace is Q2 gate, blue - Q1 gate)
Last thermal image shows that now it works fine, mosfet feels itself very comfortable.
Obviously it's a circuit design issue made by MEADE, somehow it works, but mosfets life become shorter and very sensitive to input power overvoltage.
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By the way, fixed telescope eats significantly less power (current drops approximately from 300mA to 200mA). Considering this scope can work from battery, this fix will give somebody extra battery life.
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Nice, simple minimal component fix!
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Hi Ivan7enych,
I read your posts and I think there might be some issues.
The biggest issue is the "fixed" scope capture.
1. It shows Q1 bottom nfet gate is high all the time (blue trace is 11 to 12v), so Q1 is ON all the time and pulling Q1 drain to ground.
2. Then the upper pfet is ON for ~90% of the time (yellow trace gate is at 0v most of the time) .
This would short the supply for ~90% of the time (when both fets ON at the same time).
The probes must be on another location or something?
Another is this statement:
"and when Q1 opens, Q2 source jumps from +12 to 0, and that jump goes via capacitive divider (drain-gate | source-gate) to the gate, opening it and making short circuit through Q1 and Q2."
When Q1 is closed, its drain is at 0v, so Q2 drain is also at 0v (they are tied together)
When Q1 opens, its drain is floating (and its connected to a dc brush motor with inductive kicks, this will really fool a lot of engineers), Q2 source is connected to the power rail so it cannot go from 12v to 0v.
Something is misstated or connected wrong or?
I think seeing your first scope capture, either something is not normal in the circuit, probe is not on the gate, or something is not correct.
By adding the cap, that will slow the turn off of Q2, increasing its chance of shoot though (not that it is).
Thanks.
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Hi,
1st oscillogram may be not very informative, it shows only Q2 p-mosfet gate voltage in yellow, and Q3 base (blue) just to ensure Q3 is closed and not driving Q2 gate low.
Recently I remade video about Miller effect (only in russian)
https://youtu.be/cELaQHVYETM?t=942
in 15:42 I show there -
yellow - Q2 source driven by switching on\off Q1 n-mosfet.
green - Q2 gate capacitively coupled with the source and
blue current sensor above the Q2 mosfet -
What were original transistors?
It may be an original design issue, or marginal, or it might be due to using oversized replacements -- a common mistake made by novices, using lower Rds(on) on the assumption that only load conduction losses matter, forgetting that the gate only swings as fast as the driver can push it, which is evidently exceptionally slow in this case (just a pullup resistor, no turn-off logic), so we should expect it to be more sensitive to Qg than otherwise. I don't know if this is what's happened here, just a possibility.
Also suspicious that it looks like it's just running from a microcontroller (or maybe that's a proper motor driver, I don't know), so the solution could even be software in nature -- assuming the software is hackable, that is. Which ranges from complicated to nearly impossible. (Like, at best, the timing is a byte or two in memory somewhere, and simply editing that value would do. Finding where, still isn't easy, but if the MCU and firmware are known, it can be disassembled. If they provide firmware updates for example, that are raw binary or close to it, not encrypted, that can be relatively easy. Easier still if open source, but I'm guessing not. Or if the MFG were interested in making such an update, but also guessing not. Whereas if the chip is read-protected / locked, and no updates exist, a lock bypass hack is needed to read it out, which can be quite involved, ranging from glitching the supply to decapping and microprobing the die.)
Tim -
What were original transistors?
Si4947ADY Dual P-Channel 30-V
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Oh yikes... 25nC vs. 8 max Qg, for the same Rds(on)... IRF7306 is ancient!
Hold on, what Vgs(on) was that? 5 and 10V? Ah, so it is worse, but not that much worse (see Fig. 6 https://www.infineon.com/dgdl/irf7306pbf.pdf?fileId=5546d462533600a4015355f1fc421b0a ).
Si4947: https://www.vishay.com/docs/71101/71101.pdf
OK, so I would be inclined to expect similar behavior here. It's not a perfect match, but it's fairly close.
As for capacitive divider: yes, this is indeed an effect, though usually small enough not to matter. The relevant parameters are Crss (Cdg) and Ciss (Cgs + Cdg). Which, if you look at the graphs, Ciss looks almost identical to Crss, shifted up a bunch, and this is pretty much the case for modern (vertical/trench) MOS. Basically there's a constant Cgs baseline value in there, and the nonlinear (non-constant / dependent) part is simply Crss. (Likewise, Coss is Cds + Cdg; you can do the same subtraction to find Cds alone, and as it happens, Cds itself depends on Vds, hence why Coss has a steeper slope.)
Evaluating the capacitive divider is nontrivial, because of the dependency. For example in the first volt, Ciss ~ 760pF and Crss ~ 380pF (IRF7306), the difference (Cdg) being ~380pF, a ~0.5 division. Whereas up at 30V, Crss is down to ~100pF and Ciss ~ 430pF, or a divider of 100 into 330pF, a ~0.25 division. The total figure for a 0-12V swing will be somewhere inbetween, though that already gives us enough information: Vgs(th) ~ 1V, but the best-case division is 0.25 or 3V, so the poor bastard's turning on, all right(!!).
The original Si4947 has Ciss ~ 800pF and Crss ~ 250pF at 0V, dropping to ~590 and ~60pF respectively at 30V. Again we see they have similar slopes, and mentally subtract, so Cgs ~ 530pF (constant) and Cdg 60 to 250pF, for a ratio of about 0.33 to 0.1, again still rather high but certainly will dissipate less power in the same conditions.
So that does seem consistent with the observed waveform. There's a small turn-on glitch (also visible in the unused channel; this will have frequency content in the 10MHz+ range, so is easily picked up by open probes, ground clips, etc.), then it goes from about 6V, rising gradually from there (presumably the resistor doing its work). This is consistent with the 0.25-0.5 capacitive divider (indeed closer to 0.5, even at the 12V level, which is even more concerning). When the NMOS switches off, the voltage rebounds above +12V, since the capacitors have been discharged a bit during the first part.
The downside to the shunt capacitor is, it slows switching in general, which may be a problem for other phases of operation not shown here. So, I don't know about that. But if nothing is worse than what's shown here, then it is indeed an effective solution.
Another caution: low impedances in the gate-source path, tend to cause parasitic oscillation; and this is further exacerbated by the slow turn-off, which may allow it to sit there grinding away, oscillating for quite some time -- greatly increasing EMI. This can be hard to see, even with a good oscilloscope (the frequency corresponds to the G-S loop dimensions -- it can be 100s of MHz!). The easiest way to avoid this, is by damping that loop with some series resistance, just a few ohms will be enough. So, you'd need to cut a trace to do that here (if you can fit a resistor at all!). And, it's not a guarantee: perhaps the environment just isn't reactive enough to cause oscillation, or the MOSFET isn't high enough performance to start it up (PMOS have ~2.5x poorer performance than NMOS; it might indeed simply not be capable of going that fast).
The preferred design solution of course is a proper driver, or at least a BJT boosted pull-up (like this:
https://www.seventransistorlabs.com/tmoranwms/Circuits_2010/12-24_Converter.png
the 1N914 + 2N4403 part, note the 1k pull-downs in front of them; for driving PMOS, these are swapped, so, diode pointing the other way, and NPN e.g. MMBT3904). But you almost certainly won't be able to fit that on an existing PCB, so this isn't too helpful for present purposes.
So -- given the above -- the capacitor is indeed a surprisingly adequate engineered solution. The kind of thing that, it's mediocre at best, and it's stupid [it's just one component, that generally worsens performance otherwise], and it has side effects -- but when all that works out, yeh, there you have it.
Or to put it another way: if it works, it ain't stupid. Or, let's say the above analysis counts as smartening it up.
As for going the other direction, there are some better-performing types today, though they're all non-stock at DK, alas... Options include Diodes Inc. DMP3085LSD and Panjit PJL9807_R2_00001. And they're surprisingly comparable to the original in terms of Crss (overall, and steepness of slope), so it seems PMOS haven't improved much after all!
Tim