Hi,
I have a problem with my Own SDS7102V (additional Display VGA out over SDS7102). When I was measuring in a 5V circuit (PWM modulator out of a quad comparator) the edge trigger on both channels stopped working. I wanted to access the cursor menu, but I pressed the wrong button(s) - I don't know which exactly. There is a documented issue where apparently edge trigger stopped working after entering the save menu [1]. I tried the slope trigger and lo and behold: the scope triggered. Going down that trouble shooting road I tried to contact Owon (never heard back), I tried to contact the TO of the aforementioned thread (no response), so I started to reset the scope, run self calibration, restore factory defaults and firmware upgrades in different orders - no joy.
Finally, I gave in and took the scope apart. Since both channels are affected, I assume the problem is within a circuit shared between both channels.
I based my debugging on the work Christer Weinigel, who I believe is also active in this forum, and another forum member, tinhead, who reverse engineered the AFE of his scope [2]. Christer got Linux running on the scope [3] and did a lot of work figuring out the digital connections (busses, control signals) [4].
Sidenote: My AFE is different from what tinhead drew. I have neither a ADA4817 nor a ADA4932 in my AFE. Well, at least I could not find it and there are just so many ICs. Instead I have a double diode (I believe), a transistor and an unidentified device with 3 pins, and an additional AD706 in my AFE, that are not in the schematic of tinted. Christer has, as far as I can tell, the same AFE-revision as my scope, although his blog identifies UB and UC as o ADA4817 [4, 5]. But if you look close at the photograph of the PCB you can even make out that the marking of the supposed ADA4817 actually says AD706J [6]. Just an oversight/copy&paste error, I'm sure, but for the purpose of this debugging I felt I needed to clarify, just in case the error/bug is indeed in the AFE. I don't think so, because it would be funny, if the AFEs of both channels broke at the same time, but I'm not an analog expert …
Anyway, from Christer's blog post [4] I started to draw a block diagram and started to measure in the scope. My supposition was, that it likely had to do with something that is shared between both channels. I identified following shared components: the trigger level DAC BU2506FV [7] (setting the trigger level), the trigger comparator ADCM562 [8], the signal voltage offset DAC DAC8532 [9] and dual opamp AD706J [10] for buffering the the two voltage offsets, from Christer's writing. With additional measurements I finally arrived at the following block diagram:
From this point I started prodding inside the scope to figure out how it worked. Here is what I found: As noted by Christer, the scope uses LMH6518 [11] variable gain amplifiers (VGA) for signal conditioning. The main output of those VGAs goes directly to the ADC, from there to the FPGA, SoC, and finally the screen.
Because the scope displays the signal just fine, i.e. voltage is correct, time base is correct, voltage offset works, changing DIV/V works, … I assumed at this point that the main signal processing part, i.e. AFE->VGA->ADC->FPGA->SoC was fine. Nevertheless I wanted to rule out the signal offset voltage DAC DAC8532. For this purpose I hooked another scope on the digital input pins and captured the configuration command of the DAC, as I changed the offset voltage. The DAC output voltage matched the commanded voltage on both channels. This was expected, since I could see on the screen, that rotating the offset voltage knobs was having the intended effect of moving the signal on the screen up and down.
I started looking into the (edge) trigger circuit.
Sidenote: I believe slope triggering is done in the FPGA, because it requires analysis of the signal waveform. This would also explain, why the slope triggering function was unaffected.
The VGA has an auxiliary signal output, which is specifically intended for trigger circuits in oscilloscopes. Indeed the (edge) trigger circuit is fed from this output. This auxiliary output is also differential. Common mode voltage on the main signal output as well as the auxiliary output is set to 1.31V. This is in line with the common mode voltage of the ADC (1.26V - 1.33V), derived from a band-gap voltage reference.
(Sidenote: The bandage voltage output on the ADC measured 1.91V, which had me flustered for a minute. But the ADC data sheet revealed that the bandgap voltage output can be pulled to supply voltage to enable a stronger LVDS drive signal. The ADC has no common mode voltage input.)
I reverse-engineered the trigger circuit from the VGA. It seems only the positive leg of the differential signal is used for edge-triggering. The only thing which I noticed is that the common mode voltage of auxiliary output of the VGA is set to 1.31V, but on the auxiliary output I measured a common mode voltage of 1.25V. I don't know if that is relevant, though. I don't think so, but read on …
The trigger multiplexer LMH6574 [12] selects between the different edge trigger signal couplings: AC, DC, HF, and LF. They are all derived from the VGA output and simply generated via R/C filters or capacitive coupling of the trigger mux input. The trigger mux output driver has a 2x amplification, which I guess makes sense, because using just one leg of the differential VGA output signal essentially halves the signal, because the full signal would be difference between the positive and negative leg. I could not find any "proper" differential-to-single-ended conversion between the VGA and the trigger mux. The traces there are pretty visible, there are no chips with unknown functions and measuring the DC input signal to the trigger mix is the same signal that comes out of the positive leg of the VGA.
The 2x amplification of the trigger multiplexer output, results in a common mode voltage of 2.5V. This makes also sense to me, since the trigger comparator is a PECL device fed with 5V. This means a signal offset of 0V (zero volts of the signal are mid-screen at 0 DIV), results in a single-supply trigger signal of 2.5V.
Now I started feeding in the 5V 1kHz square wave from the probe compensation output, with the scope set at 1V/DIV. This resulted in a 1kHz 500mV square wave appearing on top of the 2.5V common mode voltage signal. This signal was also reaching the trigger comparator on both channels.
Now I knew how the trigger signal was generated and had a rough understanding of the signal path before the trigger comparator. The other input to the edge trigger comparator is of course the output of the trigger level DAC. Remaining in the 1V/DIV range I measured and changed the trigger level voltage. It changed 0V to 0.5V. Since the comparator input were never crossing, the comparator never generated a trigger signal.
Next, I did a bypass test. Between the trigger level DAC and the trigger comparator is an RC-filter. I desoldered the series resistor. This allowed me two tests: (1) measure the DAC output voltage when the DAC output is unloaded. The output voltage remained at the measured level. (2) I could feed an external voltage to the trigger comparator. Feeding an appropriate voltage of 2.6V (100mV above the common mode voltage) in fact resulted in triggering at the output of the trigger comparator, as well as a stable wave form on the screen of the scope! The plot thickens …
I confirmed the result of the bypass test by using the AC coupling for the trigger signal. AC coupling should remove the DC component and let only spikes at the edges of the square wave through. This was indeed what I found at the input and output of the trigger mux. With the trigger AC-coupled triggering also worked, because the trigger signal was now crossing the trigger level voltage.
Next, I validated the output of the trigger level DAC against the commanded value from it's digital interface - it matched! Now I am stuck, because the signal input to the trigger comparator is seemingly correct and the input from trigger level DAC also. Maybe it is a software issue after all and the trigger level DAC is configured for the wrong output voltage?
After all, what does the trigger level DAC output, when I set the trigger level negative? Up until now I only varied the trigger level in the positive direction, since I had a 0-5V input signal. When I moved the trigger level negative, the DAC output voltage jumped to 4V, it's reference high voltage. Increasing negative trigger levels caused the DAC output voltage to slowly decrease from 4V. Increasing it in the positive direction again, caused the DAC output voltage to rise, until it wrapped around to 0V and rising from there to 500mV again. Could it be that turning the trigger level adjust simply increments and decrements the value, with which the trigger level DAC is being fed? That would explain the wrapping around. It seems that the trigger level DAC configuration is "missing" the 2.5V DC-offset.
One funny thing I noticed is that the trigger level DAC output only wraps around when the trigger level crosses the 0 DIV mark (mid screen), not the signal level 0, in case the signal has an offset. I guess that makes sense, but my brain is mush after days of debugging this …
At this point I would like to thank whoever read this, that you have stuck around so long! I feel like I'm at the end of what I can debug. I could find no defect, yet the scope does not work properly. I know why the edge trigger does not work (trigger comparator input level do not cross), but I don't know why: is the signal offset wrong, is the trigger level DAC broken (unlikely, but I may have made a mistake …), or is the trigger level DAC configuration wrong?
Do you see any mistake I may have made so far? What else could I measure?
Maybe a brave soul with a working edge trigger is willing to open his/her/their instrument up and provide me with known good measurements?
Other ideas? Anyways, thanks again for reading this, I appreciate any help I can get. I hope I described clearly what I did and why. This is shortened account of my measurements, as I got lost in reverse-engineering the AFE … If, despite my best efforts, there are things unclear or you have suggestion or questions let me know!
PS: Full disclosure: I cross-posted from the german mikrocontroller.net forum:
https://www.mikrocontroller.net/topic/515080[1]
https://www.eevblog.com/forum/testgear/owon-sds7102v-trigger-issue/[2]
https://www.eevblog.com/forum/testgear/review-of-owon-sds7102/msg65573/#msg65573[3]
http://blog.weinigel.se/2016/05/01/sds7102-hacking.html[4]
http://blog.weinigel.se/2016/05/27/another-look-at-sds7102-hardware.html[5]
http://blog.weinigel.se/images/2016-05-27-another-look-at-sds7102-hardware/main-back-afe.jpg[6]
http://blog.weinigel.se/images/2016-05-27-another-look-at-sds7102-hardware/main-back-large.jpg[7]
https://fscdn.rohm.com/en/products/databook/datasheet/ic/data_converter/dac/bu2506fv-e.pdf[8]
https://www.analog.com/media/en/technical-documentation/data-sheets/ADCMP561_562.pdf[9]
https://www.ti.com/lit/ds/symlink/dac8532.pdf[10]
https://www.analog.com/media/en/technical-documentation/data-sheets/AD706.pdf[11]
https://www.ti.com/lit/ds/symlink/lmh6518.pdf[12]
https://www.ti.com/lit/ds/symlink/lmh6574.pdf