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The art of logic signal manipulation with analogue components (D/R/C)

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After the bouncing of views, I now tend to agree that the different voltages for input low or high are meant for guaranteed values for low or high. These are for assurance of the logic output. In reality, there will be only one single threshold voltage for both, but for this threshold, 1) there will be a spread of this between chips; and 2) input voltages that are not far away from this voltage may result in bouncing on the output, which is normally not desired.

Hyperesis characteristic is unlikely if it is not specifically stated in the datasheet (it seems too significant not to be addressed.)

In other words, in theoretical analysis – and yet practically (this sounds paradoxical!) – the mean of these two guaranteed thresholds [that is (4.5+5.5)/2=5V] may be used as the threshold for low/high.


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