| Electronics > Repair |
| Quick Repair: Standford Research PS350 5KV 5mA(Fixed but working on calibration) |
| << < (9/11) > >> |
| alm:
I think you might want to add 0x99F (in your PS350 firmware) as four bytes that define a multiplier for the current/voltage scales, since I verified them to be different between the PS310 and PS350. This is how I described it in my listing: --- Quote ---; Four byte array that defines exponents for scale adjustment for vset/vlim/ilim/itrp: input values are multiplied by 2^n after subtracting the offset but before applying the other calibration parameter. --- End quote --- This would mean the voltages were multiplied by four and the current by two to map to the DAC values according to the PS310 dump I looked at. This exactly matches the 1.25 kV vs 5 kV voltage range. I am guessing they use an 8x lower value shunt resistor to compensate for the increased current (20 mA / 8 * 2 = 5 mA). Any idea what the relevance of ulpa (last LSB of address recognized by TMS9914, 0x3a bit 7) is? There is one function (at 0x674) that checks it (and some other variables) to decide to execute RTL through gpib_rtl (aux command 0x7): --- Code: ---ROM:06C6 in a, (3Ah) ROM:06C8 bit 7, a ROM:06CA jr z, loc_6DA ROM:06CC bit 6, a ROM:06CE jr z, loc_6D1 ROM:06D0 ret ROM:06D1 ; --------------------------------------------------------------------------- ROM:06D1 ROM:06D1 loc_6D1: ; CODE XREF: gpib_something_rtl+5Aj ROM:06D1 ld a, 3 ROM:06D3 cp b ROM:06D4 jr nz, locret_6D9 ROM:06D6 call gpib_rtl --- End code --- The only thing I can come up with is a special GPIB address to configure it as talk-only, but I could find no mention of it in the manual. What other significance could the LSB have, since the address could be both odd and even? Or am I missing something about GPIB? I am reasonably familiar with using GPIB, but have never implemented a GPIB device. I have now pretty much figured out the main loop. The IRQ handler at 0x38 will update the DACs, handle some GPIB and eventually jump back to it unless it encounters a (presumably fatal) error: --- Code: ---ROM:00E3 main_loop: ; CODE XREF: sub_C3+1Bj ROM:00E3 ; irq_service+C1j ... ROM:00E3 ei ROM:00E4 call parse_gpib_commands ROM:00E7 call gpib_something_rtl ROM:00EA call check_j504 ROM:00ED call update_displays ROM:00F0 call upd_settings_checksum ROM:00F3 call do_readouts ROM:00F6 call display_readout ROM:00F9 jp main_loop --- End code --- Obviously the gpib_something_rtl is still unclear, which is where the snippet posted above came from. |
| smgvbest:
This is the definition of the ULPA bit --- Quote ---This bit shows the LSB of the last address recognized by the TMS9914A --- End quote --- this is a bit further explaination of it --- Quote ---The' edpa' bit is used to enable the dual addressing mode of the TMS9914A. It causes the LSB of the address to be ignored by the address comparator giving two consecutive primary addresses for the device. The address by which the TMS9914A was selected is indicated by the 'ulpa' bit of the Address Status Register. --- End quote --- ah, I just noticed by the schematic they attached the D0-D7 to the TMS9914A in reverse ie. D0->D7, D7->D0 (see attached) so if that is true then bit 7 is not ULPA but is REM and REM is --- Quote ---The device is in the remote state --- End quote --- |
| alm:
Ah, that explains it! Checking REM before GTL makes complete sense. I guess they reversed the connection because the TMS9914A seems backward itself (D7 is the LSB). So now the MSB on the Z80 is also the MSB on the TMS9914A. I had actually already assumed that was the case (D0 connected to the LSB) without checking the schematic when decoding the command (GTL = 0x7). |
| smgvbest:
I need to update my portmap to flip these bits around to match. |
| smgvbest:
Here's my updated port/memory map with the GPIB BIT Order fliped and just because I'm still looking at things. And the switching frequency of the 555 timer driving the HV transformer is ~39.925Khz this is fed into a flipflop then out to 2 3-Input NAND gates to drive the GATE of the 2 IFR532's level is set via the VDRIVE signal to the COMMON of the transformer. The HVOFF signal disables the output of the 2 NAND gates thus disabling the HV output. --- Code: ---MEMORY ADDRESS OF EPROM: 0000~1FFF (PROGRAM SPACE:8KB,ST M2764A) SRAM: 4000~47FF (DATA SPACE:2KB,HITACHI HM6116) IRQ_ROUTIINE: 0038h SOURCE: SHEET 6 CLK->(U610)->TIMER @ 976.56hz/0.001024ms (4Mhz/4096(U610)74HC4020) GPIB U201 -> 555 TIMER -> PIN 3 SWITCHING FREQ = 39.925Khz FOR HV TRANSFORMER SRAM ADDRESSES: SRAM_MISC = 413AH SRAM_STATUS1 = NA SRAM_STATUS2 = 401CH EPROM ADDRESSES: *IDN? STRING 000019fah: 53 74 61 6E 66 6F 72 64 52 65 73 65 61 72 63 68 ; StanfordResearch 00001a0ah: 53 79 73 74 65 6D 73 2C 50 53 ; Systems,PS 191CH GPIB OFFSETS TABLE 0000191ch: 24 35 19 2A 3B 19 48 6E 19 49 79 19 53 89 19 54 ; $5.*;.Hn.Iy.S‰.T CMD CHAR+OFFSET 0000192ch: 8F 19 56 9A 19 57 AA 19 00 ; .Vš.Wª.. 193BH GPIB COMMAND 00001935h: 44 41 43 BE 1C 00 43 4C 53 6A 1A 45 53 45 3C 1E ; DAC¾..CLSj.ESE<. CMD+OFFSET+00H 00001945h: 45 53 52 AE 1E 49 44 4E B0 19 50 53 43 72 1E 52 ; ESR®.IDN°.PSCr.R 00001955h: 43 4C 5A 1D 52 53 54 4E 1A 53 41 56 35 1D 53 52 ; CLZ.RSTN.SAV5.SR 00001965h: 45 06 1E 53 54 42 08 1F 00 56 4F 46 14 1A 56 4F ; E..STB...VOF..VO 00001975h: 4E 24 1A 00 4C 49 4D 7F 1B 4F 55 54 7E 1C 54 52 ; N$..LIM.OUT~.TR 00001985h: 50 EE 1B 00 4D 4F 44 9E 1C 00 43 4C 52 3B 1A 4D ; Pî..MODž..CLR;.M 00001995h: 4F 44 FF 1C 00 4C 49 4D 06 1B 4F 55 54 5D 1C 53 ; ODÿ..LIM..OUT].S 000019a5h: 45 54 87 1A 00 4F 52 44 ; ET‡..ORD 19FAH 000019fah: F3 CD D5 11 FB 0E 00 C3 D4 15 CD 9D 17 C2 FD 17 ; óÍÕ.û..ÃÔ.Í.Âý. 00001a0ah: 21 8D 1F 11 3C 41 01 09 00 ED B0 ; !..<A...í° 1F7BH 00001f7bh: 5A 31 33 34 ; Z134 1F7FH EPROM_VERSION_NUMBER 00001f7fh: 31 2E 33 34 ; 1.34 1F83H 00001f83h: 88 13 88 13 82 14 82 14 64 00 ; ˆ.ˆ.‚.‚.d. 1F8DH 00001f8dh: 00 00 88 13 82 14 82 14 00 00 00 00 00 00 00 00 ; ..ˆ.‚.‚......... 00001f9dh: 0E 48 0D ; .H. 1FA0H EPROM_CAL_DATA 00001fa0h: AC 09 E4 55 0B 52 C4 09 54 52 54 52 BC 09 19 52 ; ¬.äU.RÄ.TRTR¼..R 00001fb0h: 53 4E BB 09 28 52 55 4E AC 09 E6 BF E2 C1 BD 09 ; SN».(RUN¬.æ¿âÁ½. 00001fc0h: E0 C1 E4 C3 00 00 93 43 93 43 A6 09 96 55 F6 51 ; àÁäÃ..“C“C¦.–UöQ 00001fd0h: C4 09 54 52 54 52 D1 09 31 51 30 4D D0 09 52 51 ; Ä.TRTRÑ.1Q0MÐ.RQ 00001fe0h: 22 4D A6 09 12 C0 E2 C1 D2 09 78 C2 84 C4 00 00 ; "M¦..ÀâÁÒ.x„Ä.. 00001ff0h: 93 43 93 43 00 00 76 CA 00 00 76 CA ; “C“C..vÊ..vÊ 1FFCH EPROM_SERIAL_NUMBER 00001ffch: 31 31 33 37 ; 1137 GPIB DAC CLS/*CLS ESE/*ESE ESR/*ESR IDN/*IDN PSC/*PSC RCLZ/*RCL RSTN/*RST SAV/*SAV SRE/*SRE STB/*STB VOF/HVOF VON/HVON LIM/ILIM OUT/IOUT TRP/ITRP MOD/SMOD CLR/TCLR MOD/TMOD LIM/VLIM OUT/VOUT SET/VSET ORD I/O ADDRESSES: U504 (A3-A5 -> A-C, A6-G1, WR->!G2A, IORQ->!G2B ) 40H: SPARE 48H:-SETS -> U407/U408 ------------------------------ BIT0: U407A / GND->U405.3 BIT1: U407B / U410.RF -> U405.3 BIT2: U408A / ANALOG_VOLTAGE BIT3: U408B / I_OUT_MONITOR BIT4: U408C / CV_SET BIT5: U408D / DV_LIM BIT6: U407C / I_LIM BIT7: U407D / I_TRIP ------------------------------ 50H:-DAC U410 12BIT DAC AD7542 50H DAC_LOW_NIBBLE 51H DAC_MID_NIBBLE 52H DAC_HIGH_NIBBLE 53H DAC_LOAD 58H:-LED U611 74HC374 ------------------------------ BIT0: L0 BIT1: L1 BIT2: L2 BIT3: -AD1/V_MON BIT4: -AD2/I_MON BIT5: -AD3/ANALOG_VOLTAGE_IN BIT6: -IO BIT7: UNUSED ------------------------------ 60H:-SEGB U606 74HC374 ------------------------------ BIT0: EDP BIT1: EG BIT2: EF BIT3: EE BIT4: ED BIT5: EC BIT6: EB BIT7: EA ------------------------------ 68H:-SEGA U609 74HC374 ------------------------------ BIT0: ODP BIT1: OG BIT2: OF BIT3: OE BIT4: OD BIT5: OC BIT6: OB BIT7: OA ------------------------------ 70H:-STROBE (STROB0-STROB5 LED) (STROB2-4 KEYBOARD SCAN OUT) ------------------------------ BIT0: STROB0 (LED) BIT1: STROB1 (LED) BIT2: STROB2 (LED,KBD) BIT3: STROB3 (LED,KBD) BIT4: STROB4 (LED,KBD) BIT5: STROB5 (LED) BIT6: STROB6 () BIT7: STROB7 () ------------------------------ 78H: MISC -> (U507,74HC374 OCTAL D-TYPE FLIP-FLOP) >CLK ------------------------------ BIT0: -SHUTDOWN BIT1: UPOK BIT2: -FLAG_RESET BIT3: -TIMER_RESET BIT4: (SPARE) BIT5: -POS BIT6: -NEG BIT7: FILTER ------------------------------ U505 (A3-A5 -> A-C, !M1->G1, A6->!G2A, IORQ->!G2B ) 00H: SPARE 08H: SPARE 10H: SPARE 18H: SPARE 20H: STATUS1 U506->74HC244 ------------------------------ BIT0: COMPARE BIT1: I_FAULT BIT2: CUR_LIM BIT3: PRI_FAULT BIT4: V_FAULT BIT5: TIMER BIT6: -J504/SET_MONITOR_SW BIT7: GND ------------------------------ 28H: STATUS2 U512->74HC244 ------------------------------ BIT0: HV_ON BIT1: HV_OFF BIT2: J501/-HV_SW_POS BIT3: J502/-HV_SW_NEG BIT4: GND BIT5: GND BIT6: GND BIT7: GND ------------------------------ 30H: -KBD ------------------------------ BIT0: KBD0 BIT1: KBD1 BIT2: KBD2 BIT3: KBD3 BIT4: KBD4 BIT5: KBD5 BIT6: KBD6 BIT7: KBD7 key press display 01 Man 02 GPIB 03 left-arrow 04 Right arrow 05 up-arrow 06 down-arrow 07 Enter 08 Select 09 STO 10 RCL 11 CLR 12 . 13 0 14 7 15 4 16 1 17 8 18 5 19 2 20 9 21 6 22 3 ------------------------------ 38H: -GPIB ------------------------------ READ 38H GPIB_INT_STATUS_0 BIT0: MAC (ADDRESS CHANGE) BIT1: RCL (REMOTE/LOCAL CHANGE) BIT2: SPAS (RSV1/2 SERVICE REQUEST) BIT3: END (LAST BYTE RECEIVED) BIT4: BO (BYTE OUT) BIT5: BI (BYTE IN) BIT6: INT1 (1 WHEN BITS 2-7 OF STATUS 0 SET) BIT7: INT0 (1 WHEN STATUS 1 BIT SET) 39H GPIB_INT_STATUS_1 BIT0: IFC (INTERFACE CLEAR) BIT1: SRQ (SERVICE REQUEST) BIT2: MA (MY ADDRESS) BIT3: DCAS (DEVICE CLEAR ACTIVE STATE) BIT4: APT (ADDRESS PASS THROUGH) BIT5: UNC (UNRECOGNIZED COMMAND) BIT6: ERR (ERROR) BIT7: GET (GROUP EXECUTE TRIGGER) 3AH GPIB_ADDRESS_STATUS BIT0: ULPA BIT1: TADS BIT2: LADS BIT3: TPAS BIT4: LPAS BIT5: ATN BIT6: LLO BIT7: REM 3BH GPIB_BUS_STATUS 3EH GPIB_CMD_PASS_THRU 3FH GPIB_DATA_IN WRITE 38H GPIB_INT_MASK_0 39H GPIB_INT_MASK_1 3BH GPIB_AUXILIARY_CMD 3CH GPIB_ADDRESS 3DH GPIB_SERIAL_POLL 3EH GPIB_PARALLEL_POLL 3FH GPIB_DATA_OUT ------------------------------ --- End code --- |
| Navigation |
| Message Index |
| Next page |
| Previous page |