Series defect on agilent 167xx boards?

[DocBen]

Hi there,

I recently acquired some used 16750a boards for my 16902a logic analyzer. Curiously some of them seem to have similar problems in the selftests:
Zoom Acquisition Chip Select Test Failed!
Chip 0: Master Clock from Chip 0 Test Failed!
Comparator Test Failed! (only one Pod connected to one Chip fails, not always the same one)

When inspecting the boards for damage I couldnt find anything odd except some small green nodules forming next to the plastic parts on the bottom. When I took them off I noticed that the adhesive material was hard as rock (should be soft I think) and some of the copper traces underneath are erroded. (really erroded not ripped off 

I think the failing selftest are related to the damage to the traces and more specifically to the clock traces (differential pair on the bottom left).
Did anybody repair a problem like this?

When looking at working cards they seem to develop the same problem. Right around the edges there are small green nodules. But the traces underneath have not been damaged (yet).

After reading
https://community.keysight.com/message/57746
is it just me or is this a common problem?

[simmconn]

The way I see it, it is a common problem, and you've found the cause. Either some chemicals in the adhesive/gasket is corrosive, or it absorbs moisture and causes corrosion. I don't see a good way to fix it as in many cases the residue of the adhesive/gasket is very difficult to remove, and repairing the broken trace/vias in a multi-layer board is no easy task. I may be pessimistic, but I think all 16500 series and 16700 series plugins with the plastic stiffener will eventually die because of this. It's just a matter of time.

Working cards may have the same corrosion, only that it has not eaten away enough copper to cause problem. I usually clean the corrosion with IPA but they some back after a while.

The 16900 series plugins use different stiffener (shorter and thinner) and adhesive (transparent instead of foam/felt like). Maybe Agilent knew something and took on a new design.

[MarkL]

simmconn is right.  This is a known problem with the adhesive on the plastic runners.  I have 20 or so of various 165xx and 167xx cards and they all have this corrosion to some degree.  It seems to be particularly pervasive on the 1675x cards.

The only fix is to remove the runners and, I also agree, clean up the board with IPA.  Do an end-to-end continuity check on all traces running under or near the runners.  Don't trust if they look "ok".  I've had some where the traces look fine and later found out they were corroded and severed *under* the solder mask.  I've seen some with corrosion down the vias, which could render the board unrepairable.

I've also seen boards where people have not been careful about inserting it into a chassis and there are cracked/broken components and PCB traces on the underside.  Do a thorough survey under a microscope.  One of my boards had an invisible fracture in a ferrite bead which cut the power to a chip, which in turn killed the acquisition clock.

I have a 16702B chassis which runs HPUX.  On it there's a command line utility, /usr/sprockets/bin/pv, which is the equivalent of the self-test GUI tool.  It can be used to turn on more verbose output from the self-test routines (set debug, mode, and/or result levels to something other than 0).  Some of these values can also be set from the GUI under the "Options" menu on the self-test.  I have no experience with the 16902A, but I would poke around for something similar.

Regrettably, there's no documentation for any of the verbose self-test levels or the meaning of the output.  You have to just play with it and guess as to the meaning.  However, I found that some of the output, at least under HPUX, will actually point you to specific chips or signal lines that aren't behaving as expected.  It's better than nothing.

That all being said, it's not guaranteed you can fix one of these boards.  I still have a bunch of dead ones even after fixing all the severed traces I could find.  If you bought it as "Used", I would consider returning it since it's supposed to be functional.  It can turn into a huge time sink.

EDIT: For the curious: Added photos of a 16755A with a severed trace (fixed now), and a picture of the corrosion.

[DocBen]

Great!

Well, not great, but I thought I'd been cheated on those boards.

I wonder if Agilent did that on purpose to limit the lifetime of their boards?

@MarkL: how did you repair them? Did you just bridge the missing part of the trace or reroute the connection entirely with wire?

I've attached a selftest log for posterity.
And I agree without actually knowing what part is tested where its hard to understand.
That and the fact that most technical information is in the Logic Analyzer Software Help File and not in the cards datasheet

All I see as pattern is clock. Except for the last 16752 which probably also has a defective memory chip I guess.
we'll see when I have time to try to repair them

[MarkL]

I wonder if Agilent did that on purpose to limit the lifetime of their boards?

I doubt it.  It took many years to manifest itself before they even knew they had a problem.

@MarkL: how did you repair them? Did you just bridge the missing part of the trace or reroute the connection entirely with wire?

The damage was too long to be bridged with solder.

I scraped the soldermask off both sides of the break until I found good solid copper instead of crumbly powder.  I then bridged the path using a single strand extracted from one conductor in a ribbon cable (around 0.12mm == 36 AWG).

Hint: Tin the tip of wire, and then use extra flux on the bare trace and the wire before tacking it in place.

Below is a photo where I repaired 15 paths in one area.  The white outline is where the runner sat, and it totally destroyed 11 or 12 of the traces directly under it.  I patched them all to be sure.  There were several other areas with breaks, but unfortunately repairing them all did not bring this particular card back to life.

[Bashstreet]

beautiful work.. not your first repair  Nice job shame the card had other issues 

[NickAmes]

I'm having a similar issue with a 16760A card. It fails some self-tests and there were green nodules of corrosion around the bumpers. None of the traces underneath are broken, but some vias are corroded. There seem to be two types of vias: small tented ones and large tinned ones (probably used as test points). The tinned ones are the only type corroded. Backlighting the board shows these are plane connections or blind vias. Anyone have advice on fixing these?

Here's the output from pv:

Code: [Select]

Mod A  : (0x36) 16760A Logic Analyzer (Master)
Summary   Test Name                      #Tests #Fails
------------------------------------------------------
passed    cpldRegTest                         1      0
passed    testLoadFPGA                        1      0
passed    fpgaRegTest                         1      0
passed    dataBusTest                         1      0
passed    addrBusTest                         1      0
passed    hwMemoryCellTest                    1      0
passed    unloadTest                          1      0
passed    dmaTest                             1      0
passed    sleepTest                           1      0
untested  searchTest                          0      0
passed    chipRegTest                         1      0
passed    anlyBusTest                         1      0
passed    clksTest                            1      0
passed    measAnlyBusTiming                   1      0
passed    bpClkTest                           1      0
passed    icrTest                             1      0
passed    flagTest                            1      0
passed    armTest                             1      0
passed    eepromTest                          1      0
passed    adcTest                             1      0
passed    probeIdTest                         1      0
FAILED    gaProgTest                          1      1
passed    cmpProgTest                         1      0
FAILED    dataPassThruTest                    1      1
FAILED    dataDemuxTest                       1      1
FAILED    vOffsetTest                         1      1
passed    cmpDelayTest                        1      0
FAILED    comparatorCalTest                   1      1
passed    laxCalTest                          1      0

I haven't been able to finish the searchTest. Either it's causing pv to hang or it just takes a really long time. I'm currently letting it grind away to see it it completes.

Edit: The search test still hasn't completed after two hours. pv prints the following at the start then waits:

Code: [Select]

pv> d d=9 r=9  
debugLevel=9, mode=0, resultLevel=9
pv> x searchTest

  -- Testing chip 9 slot A ...
  -- Re-Loading Acquisition Memory for Walking 1/0 tests
  -- Starting Walking 1/0 Tests
    -- Walking Zeroes test
    startRow.port:0x0.0, endRow.port:0x7e6.8
    maskSize:12, relative:1, mode:0, type:0
    search master = Chip9, FPGA0
    chip9: level:0x1,25520140 care:0x1,a55aa55a
    chip8: level:0x0,00000000 care:0x0,00000000

[Bashstreet]

If not already i would first clean up the area at 520 (right side) much as possible with stiff tooth brush (anti static one if you have) and some isopropyl (generally well tolerated but you can test first in some safe spot.

At least this should prevent any further corrosion forming.

That said i do not think the problem is causes by this particular area (of course as part of organized diagnosis it must be ruled out)

I am somewhat suspicious of the solder mask in other areas as it seems there is corrosion forming in several areas under it.
I would do a very close inspection with magnifying class (or if you have suitable microscope) on the whole board especially at the formed nodules.
This is difficult as under the solder mask (what can hide many sins) the via might be corrupted or damaged and look fine outwardly...

Any case i recommend looking for service manual It can help you get the ballpark area of problem and you can then concentrate you efforts there.

Also please take high res images of the the whole board for us to look at.  also do topside pictures and inspection if not done.

[DocBen]

Yeah, it seems the selftest is nice but doesn't really pinpoint the area or traces one needs to be concerned about.

It does seem the 16750s have a JTAG connector right next to one of the FPGAs close to the backplane connector.
I measured the connections and it seems the connections are indeed JTAG (haven't verified yet need datasheets), but I couldnt find any further connections for a JTAG chain. Maybe thats done differently.

The mainframe must be able to reprogram the cards and the source files are in Logic Analyzers Software directory (ttf / rbt / bit / xsvf files for various cards Fatcat (16910) / Fastcat (?) / Wildcat (16950 also likely 16753/54/55) and 1696x as far as I could identify).
There are others: Yari and Daytona that also come with a suffix Pv (= Performance Verification)

Daytona maybe 16760A but there are two revisions
Yari = 16750A/51A/52A
Yari Rev 2 probably = 16740A/41A/42A/50/B/51B/52B (could be verified by modifying the resistor field accordingly 4xA <-> 5xB ) See https://www.eevblog.com/forum/testgear/hpagilent-1675x-logic-analyzer-card-memory-up-hack/
agYariMemFpga.rbt is most likely for the 4 memory controllers in the middle of the card. The files are even humanreadable (well semi: 0s and 1s
agYariIfaceFpga.ttf is most likely for the Flex 10K10 (15 KB * 4 for plaintext encoding,only sram (=no persistence), there are no configuration devices on the board)

What about the rest?
I couldn't find a file for the EPM7256A so that is probably programmed via the JTAG connector in the factory. This most likely determines the basic identity of the card (Family / ID Code), the resistors determine the exact model/options.
It is probable that the EPM7256A then routes information from the backplane to program the Flex 10K10 (most likely interface logic to read out the memory) and the FPGAs on board (memory controllers, the 4 silver chips in the middle for 16750A), the two Chips with heatsinks are probably also ASICs as there are no files to program them. Then ASICs for FISO maybe A/D maybe Zoom (5 on the 16750) and last not least programmable comparators (4 top / 4 bottom).
There is an additional TTL to BTL transceiver TI FB2040 close to the backplane connector (for what?)
There is an PCF8584 close to the JTAG connector, but not connected to it -> Probe identification?

Has anybody ever tried JTAG and got it working?
Then a boundary scan would be possible making life easier.

P.S. Sorry if this post looks weird, work in progress. Help is welcome, maybe you can answer one of the questions?

[MarkL]

...
Edit: The search test still hasn't completed after two hours. pv prints the following at the start then waits:
...

Although some corrosion, your board doesn't look too terrible.

It would be nice to know what a working pv self-test looks like for a 16760A.  I don't have one to be able to help you with that, but maybe someone with the card and a 1670xA/B can run the test.

With the 1756x 1675x cards, some of the debug printout references to "Chip x" means "Ux".  If true here, there could be an issue related to U8.  All 0's looks strange.  Perhaps focus on that area and all the connecting traces to and from that area.

And yes, a high-res photo of both sides could help.  Occasionally someone can spot something that was overlooked.

If you haven't read it yet, go through the Service Guide Self Test and Theory sections.  Although there's no schematics (much grumbling here), there's sometimes useful clues:

  http://literature.cdn.keysight.com/litweb/pdf/16760-97013.pdf

I think you're right that some of the "vias" are actually test points.  I haven't attempted a repair of a via, mainly for the reason there's no schematics to verify where the signal is supposed to go.  If you have a working board to compare against, it's possible to figure it out, but be prepared to invest a large amount of time.

Why was "searchTest" showing up as untested?  Did you run the tests manually one by one?  Perhaps play with different values for debug, result, or mode.  Maybe it will print out more detail of what it's doing for searchTest.  Also, if you set debug mode 1 and then type help, does anything extra show up for the 16760A card?


EDIT: Typo on card model.

[NickAmes]

The photos won't fit within the forum size limits, so I made an imgur album: https://imgur.com/a/4dNcX (If you want, you can download the whole album using the ... menu at the bottom of the page.)

After scraping away the hardened foam, I cleaned the bumper areas with acetone using a brush and q-tips. Isopropyl alcohol didn't seem to touch it. The soldermask scratches across the traces are from chipping away the foam (there are also small particles of foam stuck to the board).

I've tested trace continuity in the areas marked OK and the center one. There's a few more corroded vias in the upper-left area. (When looking at the whole-board bottom view.) There's also some corrosion on the lids of the memory controller FPGAs, which is a bit alarming. However, the solder around them doesn't seem to be corroded.

With the 1756x 1675x cards, some of the debug printout references to "Chip x" means "Ux".  If true here, there could be an issue related to U8.  All 0's looks strange.  Perhaps focus on that area and all the connecting traces to and from that area.

If you haven't read it yet, go through the Service Guide Self Test and Theory sections.  Although there's no schematics (much grumbling here), there's sometimes useful clues:

Why was "searchTest" showing up as untested?  Did you run the tests manually one by one?  Perhaps play with different values for debug, result, or mode.  Maybe it will print out more detail of what it's doing for searchTest.  Also, if you set debug mode 1 and then type help, does anything extra show up for the 16760A card?

"Chip 8" meaning U38 make a lot of sense. I wish the problems were just confined to chip 8. If so, it might be possible to use half the logic analyzer channels. (The service manual implies that they're mostly independent.) Unfortunately, the failing self tests talk about chip 8 and 9:

Code: [Select]

pv> x dataPassThruTest
Slot A: Walking Zeros Test ...
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ .......B  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ......B.  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ......BB  Data Levels
    Slot A, Chip 8: . ........ ........  B BB...... ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . .B...... ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . B....... ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  B ........ ........  Data Levels
Slot A: Walking Ones  Test ...
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ .......B  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ......B.  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ......BB  Data Levels
    Slot A, Chip 8: . ........ ........  B BB...... ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . .B...... ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . B....... ........  Data Levels
    Slot A, Chip 9: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 8: . ........ ........  . ........ ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  B ........ ........  Data Levels
> Slot A: Data Path Pass-Thru Test Failed!
Mod   A: TEST FAILED       # "dataPassThruTest" (2, 2, -1)
pv> x dataDemuxTest
Slot A: Data Set Low ...
    Slot A, Chip 9: . ........ ......BB  . ........ ......BB  No Activity
    Slot A, Chip 8: B BB...... ........  B BB...... ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 8: . ........ ........  . ........ ........  Data Levels
    Slot A, Chip 9: . ........ ......BB  . ........ ......BB  No Activity
    Slot A, Chip 8: B BB...... ........  B BB...... ........  No Activity
    Slot A, Chip 9: . ........ ......BB  . ........ ........  Data Levels
    Slot A, Chip 8: B ........ ........  B ........ ........  Data Levels
Slot A: Data Set High ...
    Slot A, Chip 9: . ........ ......BB  . ........ ......BB  No Activity
    Slot A, Chip 8: B BB...... ........  B BB...... ........  No Activity
    Slot A, Chip 9: . ........ ......BB  . ........ ......BB  Data Levels
    Slot A, Chip 8: B BB...... ........  B BB...... ........  Data Levels
    Slot A, Chip 9: . ........ ......BB  . ........ ......BB  No Activity
    Slot A, Chip 8: B BB...... ........  B BB...... ........  No Activity
    Slot A, Chip 9: . ........ ........  . ........ ......BB  Data Levels
    Slot A, Chip 8: B ........ ........  B BB...... ........  Data Levels
> Slot A: Data Path Demux Test Failed!
Mod   A: TEST FAILED       # "dataDemuxTest" (1, 1, -1)
pv> x comparatorCalTest 
  Mod A: Pod 1, vDac1:4.700V, vAdc1:4.699V
                vDac2:0.300V, vAdc2:0.300V
                vDiff:0.001V, rProbe:0.000 KOhms, tolerance:5.0%
  Mod A: Pod 2, vDac1:4.700V, vAdc1:4.697V
                vDac2:0.300V, vAdc2:0.300V
                vDiff:0.003V, rProbe:0.000 KOhms, tolerance:5.0%
Slot A: OS Null cal failure, no 0, comp=3, chan=0
Slot A: OS Null cal failure, no 0, comp=3, chan=5
Slot A: OS Null cal failure, no 0, comp=3, chan=6
> Slot A: Pod 1: Offset Null Cal Failed
Slot A: RC comp cal failure, threshold error, comp=3, chan=0
> Slot A: Pod 1: RC Compensation Cal Failed
Slot A: Deskew cal failure, no 1, comp=3, chan=5
Slot A: Deskew cal failure, no 1, comp=3, chan=6
> Slot A: Pod 1: Data Deskew Cal Failed
CALIBRATION 1
chip 9: numPeriodPos = 0, numPeriodNeg = 1, psPerTapFine = 88
chip 9: lastPosTapFine = 16, firstPosTapFine = 6, fineTapTime = 880
chip 9: lastNegTapFine = 11, firstNegTapFine = 5, fineTapTime = 528
chip 9: numPeriodPos = 8, numPeriodNeg = 7, psPerTapCoarse = 1388
chip 9: fineToCoarseRatio = 16
chip 8: numPeriodPos = 0, numPeriodNeg = 1, psPerTapFine = 97
chip 8: lastPosTapFine = 12, firstPosTapFine = 7, fineTapTime = 485
chip 8: lastNegTapFine = 4, firstNegTapFine = 8, fineTapTime = -388
chip 8: numPeriodPos = 8, numPeriodNeg = 9, psPerTapCoarse = 1558
chip 8: fineToCoarseRatio = 16
Slot A: Tap Delay cal failure, no signal, comp=3
Slot A: Tap Delay cal failure, no signal, comp=3
> Slot A: Pod 1: Measure Tap Delay Cal Failed
Slot A: GA Delay reset at doneCount=3, compDelay=412, comp=2, ch=2
Slot A: GA Delay cal failure, initial out not 0, comp=3, ch=5
Slot A: GA Delay cal failure, initial out not 0, comp=3, ch=6
Slot A: comp:3 chan:5 cmpDelay=411 gaDelay[0]=12
Slot A: comp:3 chan:5 cmpDelay=411 gaDelay[1]=18
Slot A: comp:3 chan:5 cmpDelay=411 gaDelay[2]=26
Slot A: comp:3 chan:5 cmpDelay=411 gaDelay[3]=30
Slot A: comp:3 chan:6 cmpDelay=395 gaDelay[0]=12
Slot A: comp:3 chan:6 cmpDelay=395 gaDelay[1]=18
Slot A: comp:3 chan:6 cmpDelay=395 gaDelay[2]=26
Slot A: comp:3 chan:6 cmpDelay=395 gaDelay[3]=30
Slot A: comp:3 chan:7 cmpDelay=394 gaDelay[0]=11
Slot A: comp:3 chan:7 cmpDelay=394 gaDelay[1]=17
Slot A: comp:3 chan:7 cmpDelay=394 gaDelay[2]=24
Slot A: comp:3 chan:7 cmpDelay=394 gaDelay[3]=28
> Slot A: Pod 1: Gate Array Delay Cal Failed
> Slot A: Pod 1: Comparator Calibration Failed
Slot A: OS Null cal failure, no 0, comp=3, chan=0
Slot A: OS Null cal failure, no 0, comp=3, chan=1
Slot A: OS Null cal failure, no 0, comp=3, chan=2
Slot A: OS Null cal failure, no 0, comp=3, chan=3
> Slot A: Pod 2: Offset Null Cal Failed
Slot A: RC comp cal failure, threshold error, comp=3, chan=0
> Slot A: Pod 2: RC Compensation Cal Failed
Slot A: Deskew cal failure, no 1, comp=3, chan=1
Slot A: Deskew cal failure, no 1, comp=3, chan=2
Slot A: Deskew cal failure, no 1, comp=3, chan=3
> Slot A: Pod 2: Data Deskew Cal Failed
CALIBRATION 2
chip 9: numPeriodPos = 0, numPeriodNeg = 1, psPerTapFine = 90
chip 9: lastPosTapFine = 15, firstPosTapFine = 7, fineTapTime = 720
chip 9: lastNegTapFine = 11, firstNegTapFine = 6, fineTapTime = 450
chip 9: numPeriodPos = 8, numPeriodNeg = 7, psPerTapCoarse = 1390
chip 9: fineToCoarseRatio = 15
chip 8: numPeriodPos = 0, numPeriodNeg = 1, psPerTapFine = 97
chip 8: lastPosTapFine = 11, firstPosTapFine = 8, fineTapTime = 291
chip 8: lastNegTapFine = 4, firstNegTapFine = 9, fineTapTime = -485
chip 8: numPeriodPos = 8, numPeriodNeg = 9, psPerTapCoarse = 1561
chip 8: fineToCoarseRatio = 16
Slot A: Tap Delay cal failure, no signal, comp=3
Slot A: Tap Delay cal failure, no signal, comp=3
> Slot A: Pod 2: Measure Tap Delay Cal Failed
Slot A: GA Delay cal failure, initial out not 0, comp=3, ch=1
Slot A: GA Delay cal failure, initial out not 0, comp=3, ch=2
Slot A: GA Delay cal failure, initial out not 0, comp=3, ch=3
Slot A: comp:3 chan:1 cmpDelay=59936 gaDelay[0]=12
Slot A: comp:3 chan:1 cmpDelay=59936 gaDelay[1]=18
Slot A: comp:3 chan:1 cmpDelay=59936 gaDelay[2]=26
Slot A: comp:3 chan:1 cmpDelay=59936 gaDelay[3]=30
Slot A: comp:3 chan:2 cmpDelay=17200 gaDelay[0]=12
Slot A: comp:3 chan:2 cmpDelay=17200 gaDelay[1]=18
Slot A: comp:3 chan:2 cmpDelay=17200 gaDelay[2]=26
Slot A: comp:3 chan:2 cmpDelay=17200 gaDelay[3]=30
Slot A: comp:3 chan:3 cmpDelay=0 gaDelay[0]=12
Slot A: comp:3 chan:3 cmpDelay=0 gaDelay[1]=18
Slot A: comp:3 chan:3 cmpDelay=0 gaDelay[2]=26
Slot A: comp:3 chan:3 cmpDelay=0 gaDelay[3]=30
Slot A: GA Delay reset at doneCount=1, compDelay=399, comp=4, ch=7
> Slot A: Pod 2: Gate Array Delay Cal Failed
> Slot A: Pod 2: Comparator Calibration Failed
Mod   A: TEST FAILED       # "comparatorCalTest" (1, 1, -1)
pv> x gaProgTest 
  Slot A: GateArray[3] failed on 6/13 bits
             exp: 0x1555  act: 0x1fff
> Slot A: Gate Array Load Test Failed!
  Slot A: GateArray[3] failed on 10/13 bits
             exp: 0x1210  act: 0x1fff
> Slot A: Gate Array Load Test Failed!
  Slot A: GateArray[3] failed on 13/13 bits
             exp: 0x0000  act: 0x1fff
> Slot A: Gate Array Load Test Failed!
  Slot A: GateArray[3] failed on 13/13 bits
             exp: 0x0000  act: 0x1fff
> Slot A: Gate Array Load Test Failed!
  Slot A: GateArray[3] failed on 6/13 bits
             exp: 0x1555  act: 0x1fff
> Slot A: Gate Array Load Test Failed!
  Slot A: GateArray[3] failed on 13/13 bits
             exp: 0x0000  act: 0x1fff
> Slot A: Gate Array Load Test Failed!
  Slot A: GateArray[3] failed on 13/13 bits
             exp: 0x0000  act: 0x1fff
> Slot A: Gate Array Load Test Failed!
Mod   A: TEST FAILED       # "gaProgTest" (1, 1, -1)

"searchTest" is untested because I haven't been able to get it to complete. Running it in mode 1 doesn't change the output:

Code: [Select]

pv> d m=1 r=9 d=9
debugLevel=9, mode=1, resultLevel=9
pv> x searchTest

  -- Testing chip 9 slot A ...
  -- Re-Loading Acquisition Memory for Walking 1/0 tests
  -- Starting Walking 1/0 Tests
    -- Walking Zeroes test
    startRow.port:0x0.0, endRow.port:0x7e6.8
    maskSize:12, relative:1, mode:0, type:0
    search master = Chip9, FPGA0
    chip9: level:0x1,25520140 care:0x1,a55aa55a
    chip8: level:0x0,00000000 care:0x0,00000000

[DocBen]

The power regulator(?) next to them looks fishy. That side also looks like there significantly more dirt/corrosion (underside of the board) maybe you could clean that area some more to get a better picture.

I've used the plexiglas part of the spacers to remove the adhesive, they dont leave scratchmarks on the board.

[DocBen]

Whats throwing me off here is that the naming conventions of the chips is so different.
I wonder if thats because of the card or the analyzer.

At first I thought Chip 8/9 might refer to the 10 Chips closer to the input, but reading it more thoroughly they seem to correspond to Chip 0/1 on the 16750 with the 16902a (which dont have any correlation with the markings on the board).

If so there might be something wrong with the chip itself and not the traces, because it seems there is also trouble programming it.
Also there is something wrong with Comparator 3 maybe severed lines, but then again: which one them is Comparator 3?
Other than that all signals that dont fail the selftest could still work.
Maybe test that with a function generator?

[NickAmes]

Other than that all signals that dont fail the selftest could still work.
Maybe test that with a function generator?

Unfortunately the software hangs when trying to capture from the device. I think it's related to the searchTest failure (or maybe the gate array programming failure).

[DocBen]

@NickAmes: unfortunately that might really mean you cant use the card at all, because Chip 8/9 are ASICs so if they dont work thats propably it because they share the workload in all configurations AFAICT.
Unless you can find another card and replace the defective chip.

But that is going to be hard: I have a 16960a that I'm hoping to restore and looked at the ASIC. Not only is it BGA but they also put some sort of Epoxy around the base of it so that it is essentially glued to the board with little chance of removing it.
(I know that it isn't defective though, the Analyzer just bricked it trying to do an firmware update of the onboard interface FPGA and I think I can reprogram that or the configuration device to be more precise)

[MarkL]

Here's something that may or may not help...

On the 16700 HPUX-running chassis, you can turn on debugging when invoking the top level GUI, /usr/sprockets/bin/vp:

  usage: vp [-debugqfxa]
       [-debug level]
       [-all] (load all shared library groups)
       [-q] (don't show intro screen, don't prebuild instrument menus)
       [-f cfgfile] (load this config file at powerup)
       [-x] (exit after powerup, typically used w/ -f option)
       [-a address]
           address < 0:     don't load instruments
           address > 5:     search all scsi addresses (the default)
           address = 0-5:   search only this scsi address

Setting -debug to something greater than 1 (well, I tried 1, 2 and 255; try others if you like), makes a "Debug" option appear under the main "Select" menu for some models of analyzer cards.  I tried this on 16752A and 16756A cards, and I think it should would work on a 16760A since it appears to share some of the same code.  See screen captures below.

Perhaps you can use this to characterize the problem further by reading registers, or maybe by verifying chip select lines are working.  The "Chip Dump" button causes a file to be created in whatever directory you started "vp".  The file created contains a series of register dumps.

Setting "vp -debug 255" causes more stuff to be printed, but seems mostly related to the various widget settings for the GUI.  There's also some interesting commands if you run /usr/sprockets/bin/starhw.  I think it's the CLI equivalent to what's visible with vp -debug.

The above usage output from vp also implies the cards are accessed through some kind of emulated SCSI interface?  I really haven't looked at it in detail.

As is par for the course in more recent Agilent/Keysight equipment, there's no documentation for any of this.  Good luck, and if you discover anything useful, like for other values of -debug, please share.

There's lots of opportunity for "infinite monkey" hacking...

[DocBen]

Wow that SCSI bit is realy interesting. In the documentation they write something like propriatary multiplexed 16-bit bus.
The LA connector has 72 pins, SCSI 50 or 68 if I remember correctly, but definitly close enough.

Would really be quite ingenious to do it that way because all the ip for the fpgas would already been there and tested.

Also quite impressed with the debug options, havent had time to see if the 16902a has something like that as well, would be really helpful.

[NickAmes]

On the 16700 HPUX-running chassis, you can turn on debugging when invoking the top level GUI, /usr/sprockets/bin/vp:

  usage: vp [-debugqfxa]
       [-debug level]
       [-all] (load all shared library groups)
       [-q] (don't show intro screen, don't prebuild instrument menus)
       [-f cfgfile] (load this config file at powerup)
       [-x] (exit after powerup, typically used w/ -f option)
       [-a address]
           address < 0:     don't load instruments
           address > 5:     search all scsi addresses (the default)
           address = 0-5:   search only this scsi address

That's really interesting. Using

Code: [Select]

vp -debug 255

yields a debug menu on the 16760A. (Screenshots attached. The comparator window has a few more options than the 16756A.) I was incorrect earlier when I wrote about the app locking up when capturing from the card. It runs just fine, but locks up when trying to view the data. When trying to capture and view pod 1, the following message is printed to the console:

Code: [Select]

KatanaHardware::ramSearchStart()
    startSample:33554026, stopSample:33554824
    startRow.port:0x142550.a, endRow.port:0x1425b4.8
    maskSize:6, relative:1, mode:1, type:0
    search master = Chip9, FPGA0
    chip9: level:0x0,00009838 care:0x0,ffff0045

For pod 2:

Code: [Select]

chip 8: fineToCoarseRatio = 16
  KatanaHardware::ramSearchStart()
    startSample:33554018, stopSample:33554816
    startRow.port:0x3fffce.2, endRow.port:0x400032.0
    maskSize:6, relative:1, mode:1, type:0
    search master = Chip9, FPGA0
    chip8: level:0x0,00009838 care:0x0,ffff5a44

Also, some of the bits are oscillating with no cables attached. (Third screenshot.) They looking like they might be physically adjacent on the card.

I can't mess with the threshold settings since I don't have a probe to go on the end of the cable. According to the service manual, the LA communicates with the probe over I2C to identify which type it is. Does anyone have information on what the LA expects to find there? (Perhaps a small EEPROM?) This would also be helpful for people who can't afford the 90-pin probe prices.

[MarkL]

Wow that SCSI bit is realy interesting. In the documentation they write something like propriatary multiplexed 16-bit bus.
The LA connector has 72 pins, SCSI 50 or 68 if I remember correctly, but definitly close enough.

Would really be quite ingenious to do it that way because all the ip for the fpgas would already been there and tested.

Also quite impressed with the debug options, havent had time to see if the 16902a has something like that as well, would be really helpful.

I think now my guess about using SCSI is probably wrong.  I wasn't able to make the "vp -a" option do anything different, plus I also found some utilities that look like they're using PCI to talk to the cards.  "pciinfo", for one:

  # pciinfo
 
  Starship PCI Device Configuration Header
     0x00: 1650103c   0x10: 0000ff01   0x20: f0f00000   0x30: 00000000
     0x04: 00000007   0x14: f0dfe000   0x24: 00000000   0x34: 00000000
     0x08: 06800000   0x18: f0dff000   0x28: 00000000   0x38: 00000000
     0x0c: 0000f800   0x1c: f0e00000   0x2c: 00000000   0x3c: 00ff0104
 
  Starship PCI Device Non-Volatile Serial ROM Contents
     0x00-0x0f: 3c 10 50 16 00 e0 00 00 00 00 80 06 00 f8 00 00
     0x10-0x1f: c1 ff e8 10 00 f0 ff 7f 00 f0 ff 7f 00 00 f0 7f
     0x20-0x2f: 00 00 f0 bf 00 00 00 00 00 00 00 00 00 00 00 00
     0x30-0x3f: 00 00 00 00 00 00 00 00 00 00 00 00 ff 01 ff 00
 
  Starship PCI Base Addresses
  Base  Start     Size    Mapping     Width    Description
  ----  -----     ----    -------     -----    -----------
     0  0000ff01  40      Kernel Map  32 bits  AMCC Internal Registers
     1  f0dfe000  1000    User Map     8 bits  PassThru0-Bus FPGA
     2  f0dff000  1000    User Map     8 bits  PassThru1-Bus Registers
     3  f0e00000  100000  User Map     8 bits  PassThru2-8 Bit Memory-Mapped Bus
     4  f0f00000  100000  User Map    16 bits  PassThru3-16 Bit Memory-Mapped Bus
 
  Starship PCI AMCC Register Contents
     00=00000000 Outgoing Mailbox 1
     04=00000000 Outgoing Mailbox 2
     08=00000000 Outgoing Mailbox 3
     0c=00000000 Outgoing Mailbox 4
     10=00000000 Incoming Mailbox 1
     14=00000000 Incoming Mailbox 2
     18=00000000 Incoming Mailbox 3
     1c=00000000 Incoming Mailbox 4
     20=00000000 FIFO port
     24=00000000 Master Write Address
     28=00000000 Master Write Transfer Count
     2c=00000000 Master Read Address
     30=00000000 Master Read Transfer Count
     34=00000000 Mailbox Empty/Full Status
     38=00000000 Interrupt Control/Status Register
     3c=000000e6 Bus Master Control/Status Register
 
  Backplane State
    connectCount=1, fpgaLoaded=TRUE, fpgaVersion=1
    PCIInterruptMask=0x0000 (0000000000000000)
 
  Interrupt Setup
    Interrupts are not being used


And "pcipeek":

  # pcipeek
  Startouch Backplane Found! (frameID=1)
    PCI addresses:  PAL=f0dfe000
                    Bus control registers=f0dff000
                    Backplane 8 bit bus=f0e00000
                    Backplane 16 bit bus=f0f00000
  rockyII> ?
  RockyII peekpoke Commands: all numbers are hex
  t - toggle between 8 and 16 bit backplane bus r / w access
  r XX - read 8/16 bit backplane address XX
  w XX YY - write 8/16 bit backplane address XX with value YY
  R XXXX - read FPGA/PAL address XXXX
  W XXXX YY - write FPGA/PAL address XXXX with value YY
  T - toggle between FPGA and PAL for R / W access
  a X - set access size to 1, 2, or 4 bytes
  c NNNN - set repeat count for read/write operations
  d filename - download raw bits (.rbt or .tek) file to PCI FPGA
  m filename - download Altera (.ttf) file to Marinade FPGA
  s n - select slot n (a..j, 1..4) in cardcage.  0 ==> no slot
  D msec - delay time between I/O accesses
  v n - set verbosity level to n
  i - show PCI configuration info
  l - load backplane FPGA and list cage contents
  h, ? - this help screen
  q - quit
  rockyII> l
     A: id=0x38  Unknown hardware ID
     B: id=0x38  Unknown hardware ID
     C: id=0x35  Unknown hardware ID
     D: id=0x34  Unknown hardware ID
     E: id=0x1b  Unknown hardware ID
     F: id=0xff  Empty Slot
     G: id=0xff  Empty Slot
     H: id=0xff  Empty Slot
     I: id=0xff  Empty Slot
     J: id=0xff  Empty Slot
     1: id=0xff  Empty Slot
     2: id=0xff  Empty Slot
     3: id=0xff  Empty Slot
     4: id=0xff  Empty Slot
  rockyII>


Those id's above map back to the card product IDs in pv and other utilities.  Contents of /usr/sprockets/tools/instrument/16700/productMap (IDs are in decimal):

Code: [Select]

# This is a table of product ID codes and their corresponding HP
# product numbers. When we invent a new product (LAX for example), we'll
# need to add it to this lookup table. Until we have time to spend
# truly eliminating the code dependence cycle, this will have to do.
#
# NOTE:  the directory name and lib name must be the same, since they're
#        pulled from this file as a single name.
#

 4 16517    # Roadrunner
 5 -1       # Roadrunner expander
13 16532    # Epitaph
14 16534    # Franz
15 16535    # Talons
21 -1       # Old Pattern Generator
22 -1       # Old Pattern Generator Expander
24 -1       # Phaser expander
25 16522    # Phaser
26 -1       # Deep Phaser expander
27 16720    # Deep Phaser
31 -1       # Elan
32 16550    # Socrates
33 -1       # Socrates Expander
34 16555    # Marianas
35 -1       # Marianas Expander
36 marinade # Marinade
37 16710    # Kazon
38 -1       # Kazon Expander
40 -1       # Omega
41 -1       # Omega Expander
42 -1       # Chronicle
44 16715    # LAX
45 -1       # LAX Expander
46 ont      # ONT
47 -1       # ONT Expander
48 sfo      # SFO
49 -1       # SFO Expander
50 yakitori # YAKITORI
51 kabob    # KABOB
52 16718    # Katana
53 -1       # Katana Expander
226 multi   # Multiframe 
54 16760    # Daytona
55 -1       # Daytona Expander
56 16754    # Wildcat
57 -1       # Wildcat Expander
60 16718    # Yari/Supercharger Rev. 2
61 -1       # Yari/Supercharger Rev. 2 Expander
logic# 

More stuff to play with!

Sorry I can't be more helpful with your 16902A, but I don't think Agilent would delete all this debugging when porting the code.  I found clues for most of it by running "strings" on the executables and shared libraries, and then started trying things.  Perhaps a similar scan through the windows bits would be enlightening.

EDIT: Fixed couple of minor typos.

[MarkL]

...
Also, some of the bits are oscillating with no cables attached. (Third screenshot.) They looking like they might be physically adjacent on the card.

I can't mess with the threshold settings since I don't have a probe to go on the end of the cable. According to the service manual, the LA communicates with the probe over I2C to identify which type it is. Does anyone have information on what the LA expects to find there? (Perhaps a small EEPROM?) This would also be helpful for people who can't afford the 90-pin probe prices.

One thing you can do is buy E5378A adapters (about $20 on ebay) and some Samtec ASP-65067-01 (also on ebay or Digikey) and make your own single-ended probes.  Or with a fair amount of trouble, differential probes.  The E5378A has a resistor for the probe ID.

Unless you need the speed, extra memory, or differential probing, it might be easier in the end to go with a 16750A/16751A/16752A card with the much cheaper and ubiquitous single ended probes.  As per my other post, you can turn any of those into the maxed out 16752A.

[DocBen]

@MarkL: Great stuff, definitly keep it coming! 

I'm a little short on time right now, but I did have a look at the Logic Analyzer Software (which you can download and play with even without an Analyzer) and there doesn't seem to be anything quite like the Tools you have. Maybe thats only activated in the main application on the actual Analyzer when the module is in place. Have to test that sometime. I do wish they had linux and cli on this thing though.

Also I think the 16902a has two busses: SVY and RIO (and I think they are both named after bus stops in California, Scotts Valley and Rio Dell)
SVY seems to be the "old" 16700 type bus and RIO is an high speed addon I guess (something like LVDS with an FB2040 BTL driver) so memory transfer from the cards is likely significantly faster. But it isnt mentioned anywhere. I can only infer from an Bus tuner application for Rio (sets the voltage swing) and pci to svy / rio drivers the application installs.

Right now the first thing I want to do is to replace the electrolytic capacitors on the Mainboard and then try to get the 16740a to be a 16752b.

[DoricLoon]

I wonder if anyone could shine some light on an issue I have with a 16750A card?
Purchased 2X16741A and 2x16750A cards from Ebay advertised as not working. Price was pretty low and the cards came with cables.
I was hoping I'd be able to repair at least one of them.

The two 16741A's are pretty bad. Large number of self test fails and one of them looks like the whole bank of ram has seen high voltage? (They also show many vias with corrision)
The 16750A's are a bit more promising, one in particular. When I ran the self test it failed with a comparator error and a calibration error. Couldn't see much sign of the corrosion but took the stiffeners off anyway and had a good look (looked healthy)

I then connected a power supply linked to each of the bits of a pod and checked the thresholds based on the service manual. Pod 4 low order bits were considerably out.
Since I had plenty of spares I thought I'd steal a comparator out one of the 16741A's. At least I think I have changed the comparator? The signals enter the card and pass a couple of resistors before hitting a 44pin QFP which I assume is the comparator? (Agilent numbering so I can't search for a data sheet to verify) I checked continuity through from pod4 bit 0 to find the correct chip. After changing the said device I still have the same outcome.
Buzzed out the traces crossing under the runners without any breaks. I did however find a small section of corrosion on one of the traces about 5mm away from one of the runners. The trace was open under the corrosion. Soldered a wire bridge across it and touched up the soldering on a resistor network which looked a bit ropey.
This time when I carry out the self test the card passes with flying colours. Unfortunatley the thresholds on pod4 low order are still out of tolerance.
The error with the threshold set to -5 and 5V is around 700mV (-4.3 and 4.3V) the error reduces linearly heading toward zero. With the threshold set to zero the error is only 35mV (within the specified 65mV).
I have tested all the resitors and capacitors in the vaccinity of the comparitor. Have cross referenced with Pod 2 as well as another card and values all seem very close.

Does anyone know which devices are responsible for setting the threshold voltages? Service manual states:

 "The threshold circuit includes a precision octal DAC and precision op amp drivers. Each of the eight channels of the DAC is individually programmable which allows the user to set the thresholds of the
individual pods. The 16 data channels and the clock/data channel of each pod are all set to the same threshold voltage."

If I could identify the dac and opamp it would be a start?

The card is probably useable enough as it is. Still 56 channels working perfectly and thanks to Mark L, and the removal of one resistor and I have 32M memory depth.

[MarkL]

...
Does anyone know which devices are responsible for setting the threshold voltages?
...

I haven't done any debugging on the comparator or threshold circuits, but I would start with identifying the DAC (U39) outputs for the 8 pods.  Then compare the out-of-spec output with some of the working ones all the way to the comparators (U29 U38 U46 U53 U72 U79 U85 U88).  The DAC (U39) is an AD7841AS in a MQFP-44 and is near the backplane connector.

When you change the threshold voltage in the "Format" tab, the voltages on the DAC should change immediately, so it should be fairly easy to compare what's happening.

With a quick continuity check, it looks like the DAC output enters the comparator on pin 39, after going through a resistor divider of 7500R on top and 536R on the bottom.  Make sure the arriving DAC output and the output of the voltage divider into the comparator make sense.  Compare with the circuitry on a good pod.

I don't know what's going on inside the comparator, but keep in mind the the incoming voltages from the tip of the probe pods is arranged as a 10x probe (90k + 10k), so I would expect the threshold input of the comparator to also be in this range (just a guess - I didn't verify it).

It's difficult to probe these boards in the chassis, and you can do some checking with continuity.  But for real verification, you'll need to solder in some jumpers and run them out of the chassis to probe the voltages I'm suggesting while it's running.

If the bad pod comparator is on the bottom, you can also move the card to the bottom chassis slot, take the bottom off the chassis, and relocate the mouse/keyboard interface board (just let it hang in the air but insulate it so it doesn't short against anything).  That clears the way to probe the bottom of the board.

Please let us know what you discover!

[DoricLoon]

I haven't done any debugging on the comparator or threshold circuits, but I would start with identifying the DAC (U39) outputs for the 8 pods.  Then compare the out-of-spec output with some of the working ones all the way to the comparators (U29 U38 U46 U53 U72 U79 U85 U88).  The DAC (U39) is an AD7841AS in a MQFP-44 and is near the backplane connector.

I did notice an Analog devices chip near the backplane last night but dismissed it thinking it would be nearer the comparators. Thanks for the info. I have downloaded the datasheet for the DAC. If the reference was off then more than one 8 bit section would be affected. There are three reference connections available on the DAC but minimum of two outputs using the same ref. I guess the reference will common to all of them?

So carry out continuity checks between the DAC outputs and the resistor divider you mention. Check resistor values and connections to comparators.

Thank you Mark, will get a look at it in the evening and will update.

[MarkL]

...
If the reference was off then more than one 8 bit section would be affected. There are three reference connections available on the DAC but minimum of two outputs using the same ref. I guess the reference will common to all of them?

Yes, the DAC reference inputs are all tied together, so your assumption is correct.

So carry out continuity checks between the DAC outputs and the resistor divider you mention. Check resistor values and connections to comparators.

Right.  It could be a partially corroded trace coming from the DAC that is causing a high impedance connection to the comparator.  So it works, kind-of.

Of course it could also be the DAC itself.  Or it could also be the comparator, but you've changed that.  It's time to measure the actual voltages and compare with a known good half-pod.

Here's the mapping for the DAC outputs, which you might find useful:

  DAC (pin)    Comparator   Pod/Bits (Clock)
  ----------   ----------   ----------------
  VoutA (2)        U85       1/7:0
  VoutB (44)       U88       1/15:8 (J)
  VoutC (43)       U46       2/7:0
  VoutD (41)       U53       2/15:8 (K)
  VoutE (37)       U72       3/7:0
  VoutF (35)       U79       3/15:8 (L)
  VoutG (34)       U29       4/7:0
  VoutH (32)       U38       4/15:8 (M)

Since you're seeing problems with pod 4/7:0, I would focus your search on the path from DAC output VoutG, through the resistor divider, to U29.

Photo below of the comparator area.  They're all the same as far as the threshold input is concerned.

I'm not sure why they assigned two DAC channels per pod since the software will only set the entire pod to the same voltage.  It might be they wanted to have the option to split the pod into two different voltages in the future, or maybe there's some small differences in the comparators which are calibrated out during boot.  Dunno.