CLK, CKE, and CS# are all connected to one side of various 10k resistors on the top, and also to one side of the 33R horizontal resistor packs on the bottom.
It seems DQMH and DQML are connected together on all the chips in the group (U60, U59, U47, U51, U60, U90, U89, U87, U86), and go to one side of a blue 38R resistor on top.
It's your board, but I would not start swapping chips until I have a reason to believe it's the chip. Plus, I'm more likely to believe it's one chip that has gone bad and not both.
I would try the live probing first to see if the U50/U59 are getting the same anlyBusTest test signals that another working pair are seeing, like U23/U30. Note that the two halves of the board are practically identical copies of each other, at least for the data acquisition piece, and you can use this to your advantage for comparison purposes when you have something failing only on one half.
EDIT: A further thought on this... You should note that the memory chips all passed previous read/write tests without error. The problem appears to be when the acquisition chips are in charge of writing to the memory. The previous tests, I believe, are done through the bus interface (Altera) FPGAs.