Author Topic: Series defect on agilent 167xx boards?  (Read 38302 times)

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Offline MarkL

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Re: Series defect on agilent 167xx boards?
« Reply #50 on: December 12, 2020, 08:48:14 pm »
Also, it's worth noting that if one test fails, I've found that you should concentrate on fixing that one first.  Subsequent failures are usually a consequence of the first failure reported.
 

Offline nikodem

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Re: Series defect on agilent 167xx boards?
« Reply #51 on: December 16, 2020, 02:51:44 pm »
OK, so I wanted to update the topic. I've cleaned the whole board, and tested it again, this time using pv. It showed the same failed tests. I've found two obviously broken traces, that from the location look like there are connecting the DAC with the comparators (judging from the location etc).

After fixing the traces I've got the following result from pv:

Code: [Select]
Mod A  : (0x34) 16750A Logic Analyzer (Master)
Summary   Test Name                      #Tests #Fails
------------------------------------------------------
passed    cpldRegTest                         2      0
passed    testLoadFPGA                        2      0
passed    fpgaRegTest                         2      0
passed    dataBusTest                         2      0
passed    addrBusTest                         2      0
passed    hwMemoryCellTest                    2      0
passed    unloadTest                          2      0
passed    dmaTest                             2      0
passed    sleepTest                           2      0
passed    searchTest                          2      0
passed    chipRegTest                         1      0
FAILED    anlyBusTest                         1      1
FAILED    clksTest                            1      1
FAILED    measAnlyBusTiming                   1      1
passed    bpClkTest                           1      0
passed    cmpTest                             3      0
passed    icrTest                             1      0
passed    flagTest                            1      0
passed    armTest                             1      0
passed    calTest                             1      0
passed    zoomDataTest                        1      0
passed    zoomMasterTest                      1      0
passed    fisoRedundancyTest                  1      0
FAILED    zoomAcqTest                         17     3
passed    zoomChipSelTest                     5      0

So it seems to have fixed the cmpTest and zoomChipSelTest, but now the zoomAcqTest fails from time to time. After reseting the pv I've rerun the test 20 times and it was fine  :-// it also passed with flying colors when umaking the self-test on the device itself.

So now I have to worry only about the anlyBusTest, clksTest and measAnlyBusTiming. Does anyone has any closer information regarding those?
 

Offline MarkL

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Re: Series defect on agilent 167xx boards?
« Reply #52 on: December 16, 2020, 07:09:06 pm »
Please read Keith's and my post above about turning on debugging output for pv.  Here's another thread that talks about pv:

  https://www.eevblog.com/forum/repair/logic-analyzer-boards-repair/msg2235390/#msg2235390

There is a service guide that describes each of the tests performed.  These descriptions can provide additional clues on where to look for problems when combined with the debugging output:

  http://literature.cdn.keysight.com/litweb/pdf/16750-97003.pdf

You should also read the whole Theory of Operation chapter.  There's very little service information out there about these cards, so you need to fully absorb everything that you can.
 

Offline nikodem

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Re: Series defect on agilent 167xx boards?
« Reply #53 on: January 19, 2021, 08:33:08 pm »
OK, I've did some debugging and serious thinking  :-/O it seems, that one of the memory chips is broken(ish). My module is failing the following tests:

  • anlyBusTest - Analyzer Chip Memory Bus Test
  • clksTest - System Clocks (Master/Slave/Psync) Test
  • measAnlyBusTiming - Analyzer Memory Bus SU/H Measure[/il]
All of them use chip memory! anlyBusTest checks it directly using a walking 1 pattern and reports:

Code: [Select]
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2
for all the bits (0xFFFFFFFF) of the chip 9, port 2 of the memory. The module has 34 memory chips (48LC4M16A2 - 1Mx16x4 SDRAMs) organized in 32-bit memory. Do I assume correctly, that this means that one of the memory chips is damaged or lost its connection to the Virtex FPGAs? Do you have any idea how to check which one?  :-DMM

Regards :) and thank you for your help.
 

Offline MarkL

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Re: Series defect on agilent 167xx boards?
« Reply #54 on: January 20, 2021, 10:22:12 pm »
In the pv output "Chip 8" and "Chip 9" refer to the acquisition ASICs.

Please post (attach) your output from pv with "d r=9" turned on so we can have some context.  At the moment, the output from anlyBusTest and clksTest will do.
 

Offline nikodem

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Re: Series defect on agilent 167xx boards?
« Reply #55 on: January 21, 2021, 09:55:37 pm »
In the pv output "Chip 8" and "Chip 9" refer to the acquisition ASICs.

Please post (attach) your output from pv with "d r=9" turned on so we can have some context.  At the moment, the output from anlyBusTest and clksTest will do.

I will provide it as soon as possible, for now I only have a screenshot with d=256, r=100 of the anlyBusTest:



and part of the clksTest:



for the TEST 1: Master Clock from CHIP 9 all the clocks it's as shown:
Code: [Select]
Stage 1 is 0x0,000,0000 0x0,000,0000

for the TEST 1 I've also found this:

 

The same thing goes for TEST 2, 3, 4 and 5... the rest seems fine.

And U50 and U59 are a pair of SDRAMs on the board, that constitute a 32-bit word. They are both correctly connected to the VDD, VDDQ and VSS and have their control signals and addresses tied together (I've measured that). But I have no idea, where they should go after that. I'm guessing, that one of the control lines of the SDRAMs might be severed, and because of that, the whole bank is dead. Correct me if I'm wrong  :palm:.

The acquisition ICs are U22 and U45 (the big ones under the heatsinks)? Virtex FPGAs next to them are the glue logic to the memory?
 

Offline MarkL

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Re: Series defect on agilent 167xx boards?
« Reply #56 on: January 22, 2021, 03:25:37 am »
U45 is one of the acquisition ASIC and is known in pv as "Chip 9".

I think you're correct that the Virtex FPGAs are glue logic for the memory.

I think you're also probably right that there's a common signal for U50 and U59 that is dead and is causing them both to read as all 0's.  If so, it's probably going to be between U50/U59 and U52, or between U52 and U45.

I would examine ALL the traces on the bottom for breaks between U45 and U52.  If nothing is obvious, I would double check each trace with a continuity tester from VIA TO VIA.  You need two very fine and sharp probes to poke sideways at about a 45 degree angle into each via.  Start where you removed a runner (there's a label "AF2" there) and work your way towards the edge of the card.  You'll probably need a microscope (I do).  It's easy to lose your place, but you can mark your progress with a fine Sharpie or small removable labels.

The corrosion especially likes to attack a tiny ring of exposed copper around the small solder pads.  It's impossible to see which is why it's important to test end to end by probing the vias.

Another approach would be to turn the chassis upside down and access the card from the bottom while it's running.  You can remove the mouse/keyboard card and put it aside.  All signals, even those on top, can be probed from the bottom on the small solder pads (at least I haven't found any exceptions to this yet).  You would need to figure out which ones are CS#, WE#, CLK, RAS#, CAS#, etc. for U50/U59 with a continuity tester.

Then use a script to repeatedly run anlyBusTest.  Compare the signals on U50 and U59 with another pair of memory chips that aren't having an error.  You might be able to identify which signal(s) are missing and trace it backwards that way.

Example script that runs anlyBusTest on slot E once a second:

Code: [Select]
#!/usr/local/bin/bash

# export PVRESULTLEVEL=9
# export PVDEBUGLEVEL=9

(
  sleep 5

  while true; do
    echo "s e"
    echo "x anlyBusTest"
   
    sleep 1
  done

) | pv

I have bash loaded on my system.  I'd highly recommend it, but if you don't use it you can adapt the script for the default system shell.
 

Offline MarkL

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Re: Series defect on agilent 167xx boards?
« Reply #57 on: January 23, 2021, 04:00:33 pm »
Another thing you might try...

You'll notice that there are numerous 33R resistor networks between U52 and the memory.  They are for series termination for the control and data signals leading to the memory.  I've had several cases of open single resistors in other areas, so it might be worth checking these resistor networks.  The control signals appear to be mostly on the resistor networks directly under U52 (mounted horizontally).  The data signals appear to be mostly on the ones mounted vertically on the top and bottom.  But I would probably check them all anyway near U52 since it's very easy to do.
« Last Edit: January 23, 2021, 04:03:56 pm by MarkL »
 

Offline nikodem

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Re: Series defect on agilent 167xx boards?
« Reply #58 on: January 24, 2021, 01:03:42 am »
Another thing you might try...

You'll notice that there are numerous 33R resistor networks between U52 and the memory.  They are for series termination for the control and data signals leading to the memory.  I've had several cases of open single resistors in other areas, so it might be worth checking these resistor networks.  The control signals appear to be mostly on the resistor networks directly under U52 (mounted horizontally).  The data signals appear to be mostly on the ones mounted vertically on the top and bottom.  But I would probably check them all anyway near U52 since it's very easy to do.

I've found out, that the resistors are terminating all(?) the signals to the memory ICs, but didn't knew, that thy migh be faulty! I will check that first, as this is ultra-simple  :-DMM
 

Offline nikodem

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Re: Series defect on agilent 167xx boards?
« Reply #59 on: January 24, 2021, 07:16:37 pm »
Terminating resistors seem to be fine. I've also checked RAS, CAS, CS and WE lines, and they are fine. Still hunting for the CLK, CKE, DQMH and DQML lines - they have to be somwhere on the resistor packs :-DMM.

I'm thinking about lifting the RAMs and/or exchanging them with some else RAMs, there is pleny of them.

 

Offline MarkL

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Re: Series defect on agilent 167xx boards?
« Reply #60 on: January 25, 2021, 12:37:23 am »
CLK, CKE, and CS# are all connected to one side of various 10k resistors on the top, and also to one side of the 33R horizontal resistor packs on the bottom.

It seems DQMH and DQML are connected together on all the chips in the group (U60, U59, U47, U51, U60, U90, U89, U87, U86), and go to one side of a blue 38R resistor on top.

It's your board, but I would not start swapping chips until I have a reason to believe it's the chip.  Plus, I'm more likely to believe it's one chip that has gone bad and not both.

I would try the live probing first to see if the U50/U59 are getting the same anlyBusTest test signals that another working pair are seeing, like U23/U30.  Note that the two halves of the board are practically identical copies of each other, at least for the data acquisition piece, and you can use this to your advantage for comparison purposes when you have something failing only on one half.

EDIT:  A further thought on this...  You should note that the memory chips all passed previous read/write tests without error.  The problem appears to be when the acquisition chips are in charge of writing to the memory.  The previous tests, I believe, are done through the bus interface (Altera) FPGAs.
« Last Edit: January 25, 2021, 04:13:26 am by MarkL »
 

Offline nikodem

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Re: Series defect on agilent 167xx boards?
« Reply #61 on: January 25, 2021, 04:29:22 pm »
A further thought on this...  You should note that the memory chips all passed previous read/write tests without error.  The problem appears to be when the acquisition chips are in charge of writing to the memory.  The previous tests, I believe, are done through the bus interface (Altera) FPGAs.

From what I understand this is the first test involving memory. All further also fail.
 

Offline MarkL

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Re: Series defect on agilent 167xx boards?
« Reply #62 on: January 25, 2021, 10:02:57 pm »
A further thought on this...  You should note that the memory chips all passed previous read/write tests without error.  The problem appears to be when the acquisition chips are in charge of writing to the memory.  The previous tests, I believe, are done through the bus interface (Altera) FPGAs.

From what I understand this is the first test involving memory. All further also fail.
No.  The following tests also involve the acquisition memory and are performed before the anlyBusTest:

  dataBusTest
  addrBusTest
  hwMemoryCellTest
  unloadTest
  dmaTest
  sleepTest

You previously reported that all of these passed.
 

Offline nikodem

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Re: Series defect on agilent 167xx boards?
« Reply #63 on: January 26, 2021, 05:59:54 pm »
Indeed you are right. Is there any more documentation showing what exactly is checked by which test? On a tad lower level, so I can compare it with the hardware.

The memory ICs seem to be connected only to the Virtex FPGAs, and the lines seem to be fine. So now it's tim to check what is going on between the ASICs and the big FPGA, that controlls the offending memory chip...  :-DMM
 

Offline MarkL

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Re: Series defect on agilent 167xx boards?
« Reply #64 on: January 26, 2021, 08:06:27 pm »
Indeed you are right. Is there any more documentation showing what exactly is checked by which test? On a tad lower level, so I can compare it with the hardware.
Other than what's stated in the service guide, I'm not aware of anything.  It's clearly stated that the acquisition memory is thoroughly tested via those tests.

If you're ever in doubt, you could always lift a leg on a working memory chip and observe which tests detect it.

Quote
The memory ICs seem to be connected only to the Virtex FPGAs, and the lines seem to be fine. So now it's tim to check what is going on between the ASICs and the big FPGA, that controlls the offending memory chip...  :-DMM
I have a 16750A with one FPGA and one ASIC removed, and that is correct the memory lines only go to the FPGA.

The 16715A/16716A/16717A cards (and maybe others) have a very similar, if not identical, acquisition ASIC footprint and PCB layout as the 16750A.  And in those cards, the ASIC drives the memory directly without intervening FPGAs.  Another thing is that even though the 16750A cards have more total memory bits, the number of physical memory chips is the same (34).

My suspicion is that Agilent did not want to re-spin (or maybe make very minimal changes to) the acquisition ASIC for cost reasons and instead opted to create an adaption layer to take the memory control signals from the existing ASIC and control a larger pool of memory.

So, it may be that there is a direct correlation for the control lines to U50/U59 to one or more signals coming out of the acquisition ASIC, U45.

The acquisition ASICs in the 16715A/16A/17A do have a different part number than the 16750A, but it's also a different manufacturer ("LSI L2B1075 HP 1821-3936" vs. "Agilent L2A1509").  They may have some differences internally, but I'm looking at the footprint and how the PCB traces are arranged.


EDIT:  After looking up "L2A1509", it appears that's also made by LSI.  So the manufacturer is the same.  Minor point.
« Last Edit: January 26, 2021, 08:49:19 pm by MarkL »
 

Offline nikodem

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Re: Series defect on agilent 167xx boards?
« Reply #65 on: January 27, 2021, 10:19:15 pm »
I have read the guide etc but I have no idea how you know what is chip 9 etc.

If you're ever in doubt, you could always lift a leg on a working memory chip and observe which tests detect it.

This is one of the ideas, that I had... But not yet  >:D. Tommorow I plan to poke some more between the ASIC and the FPGA responsible for the U50/U59.

Regards!
 

Offline MarkL

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Re: Series defect on agilent 167xx boards?
« Reply #66 on: January 28, 2021, 12:32:00 am »
I have read the guide etc but I have no idea how you know what is chip 9 etc.
I fixed a lot of these boards and have decoded some of the meaning printed by pv in the process, that's all.  My failed-to-fix pile is still bigger than the fixed pile, so there's always more to learn.  Having a pool of dead cards to experiment on and (sometimes destructively) examine is also helpful.

You might want to take a look at the 16753A/54A/55A/56A service guide.  Although the board is quite different, it does use a memory controller FPGA architecture and has a slightly better explanation for some of the tests in common with the 16750A.

Quote
If you're ever in doubt, you could always lift a leg on a working memory chip and observe which tests detect it.

This is one of the ideas, that I had... But not yet  >:D. Tommorow I plan to poke some more between the ASIC and the FPGA responsible for the U50/U59.

Regards!
I already tried lifting a leg on U59 a while ago.  Attached are my notes.  Note that "Chip 9" pops up, as well as some unexpected failures since those use the acquisition memory to store test results.  The first reported problem is usually the one to concentrate on, but examining subsequent failures can sometimes provide additional information or reinforce what was already reported.

Code: [Select]
Lifted DQ1 (pin 4) of U59 (memory MT48LC4M16A2) as a test on a working
board.  Memory glue FPGA (Virtex) for that column is U52, acquisition
ASIC for that half of the board is U45.

pv> x modtests
Mod   C: TEST passed       # "cpldRegTest" (1, 0, 1)
Mod   C: TEST passed       # "testLoadFPGA" (1, 0, 1)
Mod   C: TEST passed       # "fpgaRegTest" (1, 0, 1)
Mod   C: TEST FAILED       # "dataBusTest" (1, 1, -1)
Mod   C: TEST FAILED       # "addrBusTest" (1, 1, -1)
Mod   C: TEST FAILED       # "hwMemoryCellTest" (1, 1, -1)
Mod   C: TEST FAILED       # "unloadTest" (1, 1, -1)
Mod   C: TEST FAILED       # "dmaTest" (1, 1, -1)
Mod   C: TEST FAILED       # "sleepTest" (1, 1, -1)
Mod   C: TEST passed       # "searchTest" (1, 0, 1)
Mod   C: TEST passed       # "chipRegTest" (1, 0, 1)
Mod   C: TEST FAILED       # "anlyBusTest" (1, 1, -1)
Mod   C: TEST FAILED       # "clksTest" (1, 1, -1)
Mod   C: TEST FAILED       # "measAnlyBusTiming" (1, 1, -1)
Mod   C: TEST passed       # "bpClkTest" (1, 0, 1)
Mod   C: TEST passed       # "cmpTest" (1, 0, 1)
Mod   C: TEST passed       # "icrTest" (1, 0, 1)
Mod   C: TEST passed       # "flagTest" (1, 0, 1)
Mod   C: TEST passed       # "armTest" (1, 0, 1)
Mod   C: TEST passed       # "calTest" (1, 0, 1)
Mod   C: TEST passed       # "zoomDataTest" (1, 0, 1)
Mod   C: TEST passed       # "zoomMasterTest" (1, 0, 1)
Mod   C: TEST passed       # "fisoRedundancyTest" (1, 0, 1)
Mod   C: TEST passed       # "zoomAcqTest" (1, 0, 1)
Mod   C: TEST passed       # "zoomChipSelTest" (1, 0, 1)

pv> d r=9
debugLevel=0, mode=0, resultLevel=9

pv> x dataBusTest
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=40000000, act=00000000, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFFFFE, act=BFFFFFFE, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFFFFD, act=BFFFFFFD, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFFFFB, act=BFFFFFFB, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFFFF7, act=BFFFFFF7, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFFFEF, act=BFFFFFEF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFFFDF, act=BFFFFFDF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFFFBF, act=BFFFFFBF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFFF7F, act=BFFFFF7F, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFFEFF, act=BFFFFEFF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFFDFF, act=BFFFFDFF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFFBFF, act=BFFFFBFF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFF7FF, act=BFFFF7FF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFEFFF, act=BFFFEFFF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFDFFF, act=BFFFDFFF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFBFFF, act=BFFFBFFF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFF7FFF, act=BFFF7FFF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFEFFFF, act=BFFEFFFF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFDFFFF, act=BFFDFFFF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFBFFFF, act=BFFBFFFF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFF7FFFF, act=BFF7FFFF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFEFFFFF, act=BFEFFFFF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFDFFFFF, act=BFDFFFFF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFBFFFFF, act=BFBFFFFF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FF7FFFFF, act=BF7FFFFF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FEFFFFFF, act=BEFFFFFF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FDFFFFFF, act=BDFFFFFF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=FBFFFFFF, act=BBFFFFFF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=F7FFFFFF, act=B7FFFFFF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=EFFFFFFF, act=AFFFFFFF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=DFFFFFFF, act=9FFFFFFF, Mems  U59
  Slot C, Data Failures, chip 9, bank 0, port 2, exp=7FFFFFFF, act=3FFFFFFF, Mems  U59
  Slot C, Data Error, chip 9, bank 0, port 2, bits=40000000, Mems  U59
Mod   C: TEST FAILED       # "dataBusTest" (2, 2, -1)

pv> x addrBusTest
  Slot C, chip 9, port 2, bank 0, addr=00000001, exp=FFFEFFFE, act=BFFEFFFE, Mems U59
  Slot C, chip 9, port 2, bank 0, addr=00000002, exp=FFFCFFFC, act=BFFCFFFC, Mems U59
  Slot C, chip 9, port 2, bank 0, addr=00000004, exp=FFFAFFFA, act=BFFAFFFA, Mems U59
  Slot C, chip 9, port 2, bank 0, addr=00000008, exp=FFF6FFF6, act=BFF6FFF6, Mems U59
  Slot C, chip 9, port 2, bank 0, addr=00000010, exp=FFEEFFEE, act=BFEEFFEE, Mems U59
  Slot C, chip 9, port 2, bank 0, addr=00000020, exp=FFDEFFDE, act=BFDEFFDE, Mems U59
  Slot C, chip 9, port 2, bank 0, addr=00000040, exp=FFBEFFBE, act=BFBEFFBE, Mems U59
  Slot C, chip 9, port 2, bank 0, addr=00000080, exp=FF7EFF7E, act=BF7EFF7E, Mems U59
  Slot C, chip 9, port 2, bank 0, addr=00000100, exp=FEFEFEFE, act=BEFEFEFE, Mems U59
  Slot C, chip 9, port 2, bank 0, addr=00000200, exp=FDFEFDFE, act=BDFEFDFE, Mems U59
  Slot C, chip 9, port 2, bank 0, addr=00000400, exp=FBFEFBFE, act=BBFEFBFE, Mems U59
  Slot C, chip 9, port 2, bank 0, addr=00000800, exp=F7FEF7FE, act=B7FEF7FE, Mems U59
  Slot C, chip 9, port 2, bank 0, addr=00001000, exp=EFFEEFFE, act=AFFEEFFE, Mems U59
  Slot C, chip 9, port 2, bank 0, addr=00002000, exp=DFFEDFFE, act=9FFEDFFE, Mems U59
  Slot C, chip 9, port 2, bank 0, addr=00008000, exp=7FFE7FFE, act=3FFE7FFE, Mems U59
  Slot C, chip 9, port 2, bank 0, addr=00010000, exp=FFFCFFFC, act=BFFCFFFC, Mems U59
  Slot C, chip 9, port 2, bank 0, addr=00020000, exp=FFFDFFFD, act=BFFDFFFD, Mems U59
  Slot C, chip 9, port 2, bank 0, addr=00040000, exp=FFF9FFF9, act=BFF9FFF9, Mems U59
  Slot C, chip 9, port 2, bank 0, addr=00080000, exp=FFF5FFF5, act=BFF5FFF5, Mems U59
  Slot C, chip 9, port 2, bank 0, addr=00100000, exp=FFEDFFED, act=BFEDFFED, Mems U59
  Slot C, chip 9, port 2, bank 0, addr=00200000, exp=FFDDFFDD, act=BFDDFFDD, Mems U59
  Slot C, chip 9, port 2, bank 0, addr=003FBFFF, exp=40014001, act=00014001, Mems U59
 Address bits stuck:
  Slot C, Failed address test, Memory U59
  Slot C, chip 9, port=2, bank 0, AddrBitsHigh=0004000, Mems U59 U50
Mod   C: TEST FAILED       # "addrBusTest" (2, 2, -1)

pv> x hwMemoryCellTest
  Slot C, SDRAM Fpga 0 done. Num trys = 50.
  Slot C, SDRAM Fpga 2 done. Num trys = 50.
  Slot C, SDRAM Fpga 1 done. Num trys = 74.
  Slot C, fpga U52, port 0, Failed:    Top Bank, Hi Word,  Mem U59.
  Slot C, fpga U52, port 0, Failed: Bottom Bank, Hi Word,  Mem U89.
  Slot C, SDRAM Fpga 3 done. Num trys = 74.
Mod   C: TEST FAILED       # "hwMemoryCellTest" (2, 2, -1)

pv> x unloadTest
  Slot C, Chip 9: SDRAM Data Only Unload Test ...
  Slot C, Chip 9, SDRAM U59: MAC:0x000000, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000002, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000003, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000004, bank 0, port 2 MSW, exp:0xfffb actual:0xbffb
  Slot C, Chip 9, SDRAM U59: MAC:0x000005, bank 0, port 2 MSW, exp:0xffbf actual:0xbfbf
  Slot C, Chip 9, SDRAM U59: MAC:0x000006, bank 0, port 2 MSW, exp:0xfbff actual:0xbbff
  Slot C, Chip 9, SDRAM U59: MAC:0x000008, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000009, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x00000a, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0xfffe actual:0xbffe
  Slot C, Chip 9, SDRAM U59: MAC:0x00000d, bank 0, port 2 MSW, exp:0xffef actual:0xbfef
  Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0xfeff actual:0xbeff
  Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0xefff actual:0xafff
  Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000011, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9: SDRAM Data Only Unload Test Failed!
  Slot C, Chip 9: SDRAM Count Only Unload Test ...
  Slot C, Chip 9: Interleaved Data & Count Unload Test ...
  Slot C, Chip 9, SDRAM U59: MAC:0x000000, bank 0, port 2 MSW, exp:0x54aa actual:0x14aa
  Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0x52aa actual:0x12aa
  Slot C, Chip 9, SDRAM U59: MAC:0x000002, bank 0, port 2 MSW, exp:0x4aaa actual:0x0aaa
  Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0xd555 actual:0x9555
  Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0x5555 actual:0x1555
  Slot C, Chip 9, SDRAM U59: MAC:0x00000d, bank 0, port 2 MSW, exp:0x5554 actual:0x1554
  Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0x5552 actual:0x1552
  Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0x554a actual:0x154a
  Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0x552a actual:0x152a
  Slot C, Chip 9, SDRAM U59: MAC:0x000011, bank 0, port 2 MSW, exp:0x54aa actual:0x14aa
  Slot C, Chip 9, SDRAM U59: MAC:0x000012, bank 0, port 2 MSW, exp:0x52aa actual:0x12aa
  Slot C, Chip 9, SDRAM U59: MAC:0x000013, bank 0, port 2 MSW, exp:0x4aaa actual:0x0aaa
  Slot C, Chip 9, SDRAM U59: MAC:0x00001c, bank 0, port 2 MSW, exp:0xd555 actual:0x9555
  Slot C, Chip 9, SDRAM U59: MAC:0x00001d, bank 0, port 2 MSW, exp:0x5555 actual:0x1555
  Slot C, Chip 9, SDRAM U59: MAC:0x00001e, bank 0, port 2 MSW, exp:0x5554 actual:0x1554
  Slot C, Chip 9, SDRAM U59: MAC:0x00001f, bank 0, port 2 MSW, exp:0x5552 actual:0x1552
  Slot C, Chip 9, SDRAM U59: MAC:0x000020, bank 0, port 2 MSW, exp:0x554a actual:0x154a
  Slot C, Chip 9: Interleaved Data & Count Unload Test Failed!
  Slot C, Chip 9: SDRAM Data Unload Modes Test Failed!
  Slot C, Chip 8: SDRAM Data Only Unload Test ...
  Slot C, Chip 8: SDRAM Count Only Unload Test ...
  Slot C, Chip 8: Interleaved Data & Count Unload Test ...
  Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
Mod   C: TEST FAILED       # "unloadTest" (2, 2, -1)

pv> x dmaTest
  Slot C, Chip 9: DMA Data Only Unload Test ...
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe807, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe818, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe829, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe83a, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe84b, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe85c, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe86d, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe87e, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe88f, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe8a0, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe8b1, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe8c2, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe8d3, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe8e4, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe8f5, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe906, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe917, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9: DMA Data Only Test Failed!
  Slot C, Chip 9: DMA Count Only Unload Test ...
  Slot C, Chip 9: DMA Interleaved Data & Count Test ...
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe800, bank 0, port 2 MSW, exp:0x54aa actual:0x14aa
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe801, bank 0, port 2 MSW, exp:0x52aa actual:0x12aa
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe802, bank 0, port 2 MSW, exp:0x4aaa actual:0x0aaa
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe80b, bank 0, port 2 MSW, exp:0xd555 actual:0x9555
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe80c, bank 0, port 2 MSW, exp:0x5555 actual:0x1555
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe80d, bank 0, port 2 MSW, exp:0x5554 actual:0x1554
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe80e, bank 0, port 2 MSW, exp:0x5552 actual:0x1552
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe80f, bank 0, port 2 MSW, exp:0x554a actual:0x154a
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe810, bank 0, port 2 MSW, exp:0x552a actual:0x152a
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe811, bank 0, port 2 MSW, exp:0x54aa actual:0x14aa
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe812, bank 0, port 2 MSW, exp:0x52aa actual:0x12aa
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe813, bank 0, port 2 MSW, exp:0x4aaa actual:0x0aaa
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe81c, bank 0, port 2 MSW, exp:0xd555 actual:0x9555
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe81d, bank 0, port 2 MSW, exp:0x5555 actual:0x1555
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe81e, bank 0, port 2 MSW, exp:0x5554 actual:0x1554
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe81f, bank 0, port 2 MSW, exp:0x5552 actual:0x1552
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe820, bank 0, port 2 MSW, exp:0x554a actual:0x154a
  Slot C, Chip 9: DMA Interleaved Data & Count Test Failed!
> Slot C, Chip 9: DMA Unload Modes Test Failed!
  Slot C, Chip 8: DMA Data Only Unload Test ...
  Slot C, Chip 8: DMA Count Only Unload Test ...
  Slot C, Chip 8: DMA Interleaved Data & Count Test ...
  Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
Mod   C: TEST FAILED       # "dmaTest" (2, 2, -1)

pv> x sleepTest
  Slot C, Chip 9, SDRAM U59: MAC:0x000000, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000002, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000003, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000004, bank 0, port 2 MSW, exp:0xfffb actual:0xbffb
  Slot C, Chip 9, SDRAM U59: MAC:0x000005, bank 0, port 2 MSW, exp:0xffbf actual:0xbfbf
  Slot C, Chip 9, SDRAM U59: MAC:0x000006, bank 0, port 2 MSW, exp:0xfbff actual:0xbbff
  Slot C, Chip 9, SDRAM U59: MAC:0x000008, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000009, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x00000a, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0xfffe actual:0xbffe
  Slot C, Chip 9, SDRAM U59: MAC:0x00000d, bank 0, port 2 MSW, exp:0xffef actual:0xbfef
  Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0xfeff actual:0xbeff
  Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0xefff actual:0xafff
  Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000011, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9: Top bank check failed before Sleep mode.
Mod   C: TEST FAILED       # "sleepTest" (2, 2, -1)

pv> x anlyBusTest
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=40000000, act=00000000
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFFE, act=BFFFFFFE
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFFD, act=BFFFFFFD
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFFB, act=BFFFFFFB
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFF7, act=BFFFFFF7
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFEF, act=BFFFFFEF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFDF, act=BFFFFFDF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFBF, act=BFFFFFBF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFF7F, act=BFFFFF7F
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFEFF, act=BFFFFEFF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFDFF, act=BFFFFDFF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFBFF, act=BFFFFBFF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFF7FF, act=BFFFF7FF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFEFFF, act=BFFFEFFF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFDFFF, act=BFFFDFFF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFBFFF, act=BFFFBFFF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFF7FFF, act=BFFF7FFF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFEFFFF, act=BFFEFFFF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFDFFFF, act=BFFDFFFF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFBFFFF, act=BFFBFFFF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFF7FFFF, act=BFF7FFFF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFEFFFFF, act=BFEFFFFF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFDFFFFF, act=BFDFFFFF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFBFFFFF, act=BFBFFFFF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FF7FFFFF, act=BF7FFFFF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FEFFFFFF, act=BEFFFFFF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FDFFFFFF, act=BDFFFFFF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FBFFFFFF, act=BBFFFFFF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=F7FFFFFF, act=B7FFFFFF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=EFFFFFFF, act=AFFFFFFF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=DFFFFFFF, act=9FFFFFFF
  Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=7FFFFFFF, act=3FFFFFFF
  Slot C, Analysis Chip Data Bit Error, chip 9, port 2, bits=40000000
Mod   C: TEST FAILED       # "anlyBusTest" (2, 2, -1)

pv> x clksTest
  TEST  1: Master Clock from CHIP 9 ...
  Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
  Slot C, Chip 9, SDRAM U59: MAC:0x000004, bank 0, port 2 MSW, exp:0x4926 actual:0x0926
  Slot C, Chip 9, SDRAM U59: MAC:0x000007, bank 0, port 2 MSW, exp:0x6492 actual:0x2492
  Slot C, Chip 9, SDRAM U59: MAC:0x000008, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
  Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
  Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0x4992 actual:0x0992
  Slot C, Chip 9, SDRAM U59: MAC:0x000012, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
  Slot C, Chip 9, SDRAM U59: MAC:0x000015, bank 0, port 2 MSW, exp:0x4926 actual:0x0926
  Slot C, Chip 9, SDRAM U59: MAC:0x000018, bank 0, port 2 MSW, exp:0x6492 actual:0x2492
  Slot C, Chip 9, SDRAM U59: MAC:0x000019, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
  Slot C, Chip 9, SDRAM U59: MAC:0x00001c, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
  Slot C, Chip 9, SDRAM U59: MAC:0x00001f, bank 0, port 2 MSW, exp:0x4992 actual:0x0992
  Slot C, Chip 9, SDRAM U59: MAC:0x000023, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
  Slot C, Chip 9, SDRAM U59: MAC:0x000026, bank 0, port 2 MSW, exp:0x4926 actual:0x0926
  Slot C, Chip 9, SDRAM U59: MAC:0x000029, bank 0, port 2 MSW, exp:0x6492 actual:0x2492
  Slot C, Chip 9, SDRAM U59: MAC:0x00002a, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
  Slot C, Chip 9, SDRAM U59: MAC:0x00002d, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
> Slot C, Chip 9: Master Clock from Chip 9 Test Failed!
  Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
  TEST  2: Slave  Clock from CHIP 9 ...
  Slot C, Chip 9, SDRAM U59: MAC:0x000000, bank 0, port 2 MSW, exp:0xe739 actual:0xa739
  Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0x739c actual:0x339c
  Slot C, Chip 9, SDRAM U59: MAC:0x000004, bank 0, port 2 MSW, exp:0xce73 actual:0x8e73
  Slot C, Chip 9, SDRAM U59: MAC:0x000005, bank 0, port 2 MSW, exp:0xe733 actual:0xa733
  Slot C, Chip 9, SDRAM U59: MAC:0x000006, bank 0, port 2 MSW, exp:0x7339 actual:0x3339
  Slot C, Chip 9, SDRAM U59: MAC:0x00000a, bank 0, port 2 MSW, exp:0xce73 actual:0x8e73
  Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0xe739 actual:0xa739
  Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0x739c actual:0x339c
  Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0xcce7 actual:0x8ce7
  Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0xce73 actual:0x8e73
  Slot C, Chip 9, SDRAM U59: MAC:0x000011, bank 0, port 2 MSW, exp:0xe739 actual:0xa739
  Slot C, Chip 9, SDRAM U59: MAC:0x000012, bank 0, port 2 MSW, exp:0x739c actual:0x339c
  Slot C, Chip 9, SDRAM U59: MAC:0x000015, bank 0, port 2 MSW, exp:0xce73 actual:0x8e73
  Slot C, Chip 9, SDRAM U59: MAC:0x000016, bank 0, port 2 MSW, exp:0xe733 actual:0xa733
  Slot C, Chip 9, SDRAM U59: MAC:0x000017, bank 0, port 2 MSW, exp:0x7339 actual:0x3339
  Slot C, Chip 9, SDRAM U59: MAC:0x00001b, bank 0, port 2 MSW, exp:0xce73 actual:0x8e73
  Slot C, Chip 9, SDRAM U59: MAC:0x00001c, bank 0, port 2 MSW, exp:0xe739 actual:0xa739
> Slot C, Chip 9: Slave  Clock from Chip 9 Test Failed!
  Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
  TEST  3: Master Clock from CHIP 8 thru Chip 9 ...
  Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0xb6db actual:0xf6db
  Slot C, Chip 9, SDRAM U59: MAC:0x000003, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
  Slot C, Chip 9, SDRAM U59: MAC:0x000005, bank 0, port 2 MSW, exp:0x6d9b actual:0x2d9b
  Slot C, Chip 9, SDRAM U59: MAC:0x000006, bank 0, port 2 MSW, exp:0xd9b6 actual:0x99b6
  Slot C, Chip 9, SDRAM U59: MAC:0x000009, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
  Slot C, Chip 9, SDRAM U59: MAC:0x00000a, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
  Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
  Slot C, Chip 9, SDRAM U59: MAC:0x00000d, bank 0, port 2 MSW, exp:0xdb66 actual:0x9b66
  Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0x66db actual:0x26db
  Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
  Slot C, Chip 9, SDRAM U59: MAC:0x000011, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
  Slot C, Chip 9, SDRAM U59: MAC:0x000013, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
  Slot C, Chip 9, SDRAM U59: MAC:0x000014, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
  Slot C, Chip 9, SDRAM U59: MAC:0x000016, bank 0, port 2 MSW, exp:0x6d9b actual:0x2d9b
  Slot C, Chip 9, SDRAM U59: MAC:0x000017, bank 0, port 2 MSW, exp:0xd9b6 actual:0x99b6
  Slot C, Chip 9, SDRAM U59: MAC:0x00001a, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
  Slot C, Chip 9, SDRAM U59: MAC:0x00001b, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
> Slot C, Chip 9: Master Clock from Chip 8 thru Chip 9 Test Failed!
  Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
  TEST  4: Slave  Clock from CHIP 8 thru Chip 9 ...
  Slot C, Chip 9, SDRAM U59: MAC:0x000000, bank 0, port 2 MSW, exp:0x18c6 actual:0x58c6
  Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0x8c63 actual:0xcc63
  Slot C, Chip 9, SDRAM U59: MAC:0x000002, bank 0, port 2 MSW, exp:0xc631 actual:0x8631
  Slot C, Chip 9, SDRAM U59: MAC:0x000003, bank 0, port 2 MSW, exp:0x6318 actual:0x2318
  Slot C, Chip 9, SDRAM U59: MAC:0x000007, bank 0, port 2 MSW, exp:0xcc63 actual:0x8c63
  Slot C, Chip 9, SDRAM U59: MAC:0x000008, bank 0, port 2 MSW, exp:0xc631 actual:0x8631
  Slot C, Chip 9, SDRAM U59: MAC:0x000009, bank 0, port 2 MSW, exp:0x6318 actual:0x2318
  Slot C, Chip 9, SDRAM U59: MAC:0x00000d, bank 0, port 2 MSW, exp:0xc633 actual:0x8633
  Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0x6331 actual:0x2331
  Slot C, Chip 9, SDRAM U59: MAC:0x000013, bank 0, port 2 MSW, exp:0xc631 actual:0x8631
  Slot C, Chip 9, SDRAM U59: MAC:0x000014, bank 0, port 2 MSW, exp:0x6318 actual:0x2318
  Slot C, Chip 9, SDRAM U59: MAC:0x000018, bank 0, port 2 MSW, exp:0xcc63 actual:0x8c63
  Slot C, Chip 9, SDRAM U59: MAC:0x000019, bank 0, port 2 MSW, exp:0xc631 actual:0x8631
  Slot C, Chip 9, SDRAM U59: MAC:0x00001a, bank 0, port 2 MSW, exp:0x6318 actual:0x2318
  Slot C, Chip 9, SDRAM U59: MAC:0x00001e, bank 0, port 2 MSW, exp:0xc633 actual:0x8633
  Slot C, Chip 9, SDRAM U59: MAC:0x00001f, bank 0, port 2 MSW, exp:0x6331 actual:0x2331
  Slot C, Chip 9, SDRAM U59: MAC:0x000024, bank 0, port 2 MSW, exp:0xc631 actual:0x8631
> Slot C, Chip 9: Slave  Clock from Chip 8 thru Chip 9 Test Failed!
  Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
  TEST  5: Psync  Clock from CHIP 8 thru CHIP 9 ...
  Slot C, Chip 9, SDRAM U59: MAC:0x000000, bank 0, port 2 MSW, exp:0xb6db actual:0xf6db
  Slot C, Chip 9, SDRAM U59: MAC:0x000002, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
  Slot C, Chip 9, SDRAM U59: MAC:0x000004, bank 0, port 2 MSW, exp:0x6db7 actual:0x2db7
  Slot C, Chip 9, SDRAM U59: MAC:0x000005, bank 0, port 2 MSW, exp:0xdb76 actual:0x9b76
  Slot C, Chip 9, SDRAM U59: MAC:0x000007, bank 0, port 2 MSW, exp:0x76db actual:0x36db
  Slot C, Chip 9, SDRAM U59: MAC:0x000008, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
  Slot C, Chip 9, SDRAM U59: MAC:0x000009, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
  Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
  Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
  Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0x6ddb actual:0x2ddb
  Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0xddb6 actual:0x9db6
  Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
  Slot C, Chip 9, SDRAM U59: MAC:0x000012, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
  Slot C, Chip 9, SDRAM U59: MAC:0x000013, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
  Slot C, Chip 9, SDRAM U59: MAC:0x000015, bank 0, port 2 MSW, exp:0x6db7 actual:0x2db7
  Slot C, Chip 9, SDRAM U59: MAC:0x000016, bank 0, port 2 MSW, exp:0xdb76 actual:0x9b76
  Slot C, Chip 9, SDRAM U59: MAC:0x000018, bank 0, port 2 MSW, exp:0x76db actual:0x36db
> Slot C, Chip 9: Slave  Clock from Chip 9 thru Chip 8 Test Failed!
  Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
  TEST  6: Master Clock from CHIP 8 ...
  TEST  7: Slave  Clock from CHIP 8 ...
  TEST  8: Master Clock from CHIP 9 thru CHIP 8 ...
  TEST  9: Slave  Clock from CHIP 9 thru CHIP 8 ...
  TEST 10: Psync  Clock from CHIP 9 thru CHIP 8 ...
  TEST 11: Poststore Counter Test ...
Mod   C: TEST FAILED       # "clksTest" (2, 2, -1)

pv>x measAnlyBusTiming
  Chip 9: Maximum Time Range = 6300
  Slot Chip FineT Port SuTime  WinSize SuErrBits  HldErrBits STap HTap
  ==== ==== ===== ==== ======= ======= ========== ========== ==== ====
    C    9   100   0    5600   > 700    04080002   FFFFFFFF    7    0
    C    9   100   1    5300   >1000    00000240   FFFF6DBB   10    0
    C    9   100   2       0   >6300    40000000   443A6FFF   63    0
FAILED: Slot:C Chip:9 Port:2  Setup:   0 (Limit > 3000), Setup Tap = 63 (Limit < 20), Bits:40000000
    C    9   100   3    5600   > 700    00412000   FFFFFFFF    7    0
    C    9   100   B      -1   >   0        0000       FFFF  999  999
  Chip 8: Maximum Time Range = 5985
  Slot Chip FineT Port SuTime  WinSize SuErrBits  HldErrBits STap HTap
  ==== ==== ===== ==== ======= ======= ========== ========== ==== ====
    C    8    95   0    5225   > 760    00080000   FFFFFFFF    8    0
    C    8    95   1    5035   > 950    00000240   FFFFEDBB   10    0
    C    8    95   2    4940   >1045    88000000   043A6FFF   11    0
    C    8    95   3    5320   > 665    00412000   FFFFFFFF    7    0
    C    8    95   B      -1   >   0        0000       FFFF  999  999
Mod   C: TEST FAILED       # "measAnlyBusTiming" (3, 3, -1)

------------------------------------------------------------

Some of these tests produce more info with resultLevel 10...

pv> d r=10
debugLevel=0, mode=1, resultLevel=10

pv> x unloadTest
  Slot C, Chip 9: SDRAM Data Only Unload Test ...
  -- Writing Full Channel Normal Data --
  -- Writing Normal Bonus Data --
  -- Reading Full Channel Normal Data --
  Slot C, Chip 9, SDRAM U59: MAC:0x000000, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000002, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000003, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000004, bank 0, port 2 MSW, exp:0xfffb actual:0xbffb
  Slot C, Chip 9, SDRAM U59: MAC:0x000005, bank 0, port 2 MSW, exp:0xffbf actual:0xbfbf
  Slot C, Chip 9, SDRAM U59: MAC:0x000006, bank 0, port 2 MSW, exp:0xfbff actual:0xbbff
  Slot C, Chip 9, SDRAM U59: MAC:0x000008, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000009, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x00000a, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0xfffe actual:0xbffe
  Slot C, Chip 9, SDRAM U59: MAC:0x00000d, bank 0, port 2 MSW, exp:0xffef actual:0xbfef
  Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0xfeff actual:0xbeff
  Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0xefff actual:0xafff
  Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000011, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  -- Reading Bonus Data --
  Slot C, Chip 9: SDRAM Data Only Unload Test Failed!
  Slot C, Chip 9: SDRAM Count Only Unload Test ...
  -- Writing Count Data --
  -- Reading Count Data --
  Slot C, Chip 9: Interleaved Data & Count Unload Test ...
  -- Writing Interleaved Data & Tags --
  -- Writing Interleaved Bonus Data --
  -- Reading Full Channel Normal Data --
  Slot C, Chip 9, SDRAM U59: MAC:0x000000, bank 0, port 2 MSW, exp:0x54aa actual:0x14aa
  Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0x52aa actual:0x12aa
  Slot C, Chip 9, SDRAM U59: MAC:0x000002, bank 0, port 2 MSW, exp:0x4aaa actual:0x0aaa
  Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0xd555 actual:0x9555
  Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0x5555 actual:0x1555
  Slot C, Chip 9, SDRAM U59: MAC:0x00000d, bank 0, port 2 MSW, exp:0x5554 actual:0x1554
  Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0x5552 actual:0x1552
  Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0x554a actual:0x154a
  Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0x552a actual:0x152a
  Slot C, Chip 9, SDRAM U59: MAC:0x000011, bank 0, port 2 MSW, exp:0x54aa actual:0x14aa
  Slot C, Chip 9, SDRAM U59: MAC:0x000012, bank 0, port 2 MSW, exp:0x52aa actual:0x12aa
  Slot C, Chip 9, SDRAM U59: MAC:0x000013, bank 0, port 2 MSW, exp:0x4aaa actual:0x0aaa
  Slot C, Chip 9, SDRAM U59: MAC:0x00001c, bank 0, port 2 MSW, exp:0xd555 actual:0x9555
  Slot C, Chip 9, SDRAM U59: MAC:0x00001d, bank 0, port 2 MSW, exp:0x5555 actual:0x1555
  Slot C, Chip 9, SDRAM U59: MAC:0x00001e, bank 0, port 2 MSW, exp:0x5554 actual:0x1554
  Slot C, Chip 9, SDRAM U59: MAC:0x00001f, bank 0, port 2 MSW, exp:0x5552 actual:0x1552
  Slot C, Chip 9, SDRAM U59: MAC:0x000020, bank 0, port 2 MSW, exp:0x554a actual:0x154a
  -- Reading Bonus Data --
  -- Reading Count Data --
  Slot C, Chip 9: Interleaved Data & Count Unload Test Failed!
  Slot C, Chip 9: SDRAM Data Unload Modes Test Failed!
  Slot C, Chip 8: SDRAM Data Only Unload Test ...
  -- Writing Full Channel Normal Data --
  -- Writing Normal Bonus Data --
  -- Reading Full Channel Normal Data --
  -- Reading Bonus Data --
  Slot C, Chip 8: SDRAM Count Only Unload Test ...
  -- Writing Count Data --
  -- Reading Count Data --
  Slot C, Chip 8: Interleaved Data & Count Unload Test ...
  -- Writing Interleaved Data & Tags --
  -- Writing Interleaved Bonus Data --
  -- Reading Full Channel Normal Data --
  -- Reading Bonus Data --
  -- Reading Count Data --
  Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
Mod   C: TEST FAILED       # "unloadTest" (6, 6, -1)

pv> x dmaTest
  Slot C, Chip 9: DMA Data Only Unload Test ...
  -- Writing Full Channel Normal Data --
  -- Writing Normal Bonus Data --
  -- Reading Normal Data Using DMA --
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe807, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe818, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe829, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe83a, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe84b, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe85c, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe86d, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe87e, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe88f, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe8a0, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe8b1, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe8c2, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe8d3, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe8e4, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe8f5, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe906, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe917, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
  -- Reading Bonus Data Using DMA --
  Slot C, Chip 9: DMA Data Only Test Failed!
  Slot C, Chip 9: DMA Count Only Unload Test ...
  -- Writing Count Data --
  -- Reading Count Data Using DMA --
  Slot C, Chip 9: DMA Interleaved Data & Count Test ...
  -- Writing Interleaved Data & Tags --
  -- Writing Interleaved Bonus Data --
  -- Reading Normal Data Using DMA --
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe800, bank 0, port 2 MSW, exp:0x54aa actual:0x14aa
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe801, bank 0, port 2 MSW, exp:0x52aa actual:0x12aa
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe802, bank 0, port 2 MSW, exp:0x4aaa actual:0x0aaa
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe80b, bank 0, port 2 MSW, exp:0xd555 actual:0x9555
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe80c, bank 0, port 2 MSW, exp:0x5555 actual:0x1555
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe80d, bank 0, port 2 MSW, exp:0x5554 actual:0x1554
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe80e, bank 0, port 2 MSW, exp:0x5552 actual:0x1552
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe80f, bank 0, port 2 MSW, exp:0x554a actual:0x154a
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe810, bank 0, port 2 MSW, exp:0x552a actual:0x152a
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe811, bank 0, port 2 MSW, exp:0x54aa actual:0x14aa
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe812, bank 0, port 2 MSW, exp:0x52aa actual:0x12aa
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe813, bank 0, port 2 MSW, exp:0x4aaa actual:0x0aaa
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe81c, bank 0, port 2 MSW, exp:0xd555 actual:0x9555
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe81d, bank 0, port 2 MSW, exp:0x5555 actual:0x1555
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe81e, bank 0, port 2 MSW, exp:0x5554 actual:0x1554
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe81f, bank 0, port 2 MSW, exp:0x5552 actual:0x1552
  Slot C, Chip 9, SDRAM U59: MAC:0x3fe820, bank 0, port 2 MSW, exp:0x554a actual:0x154a
  -- Reading Bonus Data Using DMA --
  -- Reading Count Data Using DMA --
  Slot C, Chip 9: DMA Interleaved Data & Count Test Failed!
> Slot C, Chip 9: DMA Unload Modes Test Failed!
  Slot C, Chip 8: DMA Data Only Unload Test ...
  -- Writing Full Channel Normal Data --
  -- Writing Normal Bonus Data --
  -- Reading Normal Data Using DMA --
  -- Reading Bonus Data Using DMA --
  Slot C, Chip 8: DMA Count Only Unload Test ...
  -- Writing Count Data --
  -- Reading Count Data Using DMA --
  Slot C, Chip 8: DMA Interleaved Data & Count Test ...
  -- Writing Interleaved Data & Tags --
  -- Writing Interleaved Bonus Data --
  -- Reading Normal Data Using DMA --
  -- Reading Bonus Data Using DMA --
  -- Reading Count Data Using DMA --
  Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
Mod   C: TEST FAILED       # "dmaTest" (2, 2, -1)

pv> x sleepTest
  -- Writing Full Channel Normal Data --
  -- Writing Normal Bonus Data --
  -- Writing Full Channel Normal Data --
  -- Writing Normal Bonus Data --
  -- Reading Full Channel Normal Data --
  Slot C, Chip 9, SDRAM U59: MAC:0x000000, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000002, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000003, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000004, bank 0, port 2 MSW, exp:0xfffb actual:0xbffb
  Slot C, Chip 9, SDRAM U59: MAC:0x000005, bank 0, port 2 MSW, exp:0xffbf actual:0xbfbf
  Slot C, Chip 9, SDRAM U59: MAC:0x000006, bank 0, port 2 MSW, exp:0xfbff actual:0xbbff
  Slot C, Chip 9, SDRAM U59: MAC:0x000008, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000009, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x00000a, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0xfffe actual:0xbffe
  Slot C, Chip 9, SDRAM U59: MAC:0x00000d, bank 0, port 2 MSW, exp:0xffef actual:0xbfef
  Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0xfeff actual:0xbeff
  Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0xefff actual:0xafff
  Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  Slot C, Chip 9, SDRAM U59: MAC:0x000011, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
  -- Reading Bonus Data --
  Slot C, Chip 9: Top bank check failed before Sleep mode.
  -- Reading Full Channel Normal Data --
  -- Reading Bonus Data --
  -- Reading Full Channel Normal Data --
  -- Reading Bonus Data --
  -- Reading Full Channel Normal Data --
  -- Reading Bonus Data --
Mod   C: TEST FAILED       # "sleepTest" (1, 1, -1)

pv> x clksTest
  -- Writing Full Channel Normal Data --
  -- Writing Normal Bonus Data --
  TEST  1: Master Clock from CHIP 9 ...
  -- Reading Full Channel Normal Data --
  Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
  Slot C, Chip 9, SDRAM U59: MAC:0x000004, bank 0, port 2 MSW, exp:0x4926 actual:0x0926
  Slot C, Chip 9, SDRAM U59: MAC:0x000007, bank 0, port 2 MSW, exp:0x6492 actual:0x2492
  Slot C, Chip 9, SDRAM U59: MAC:0x000008, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
  Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
  Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0x4992 actual:0x0992
  Slot C, Chip 9, SDRAM U59: MAC:0x000012, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
  Slot C, Chip 9, SDRAM U59: MAC:0x000015, bank 0, port 2 MSW, exp:0x4926 actual:0x0926
  Slot C, Chip 9, SDRAM U59: MAC:0x000018, bank 0, port 2 MSW, exp:0x6492 actual:0x2492
  Slot C, Chip 9, SDRAM U59: MAC:0x000019, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
  Slot C, Chip 9, SDRAM U59: MAC:0x00001c, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
  Slot C, Chip 9, SDRAM U59: MAC:0x00001f, bank 0, port 2 MSW, exp:0x4992 actual:0x0992
  Slot C, Chip 9, SDRAM U59: MAC:0x000023, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
  Slot C, Chip 9, SDRAM U59: MAC:0x000026, bank 0, port 2 MSW, exp:0x4926 actual:0x0926
  Slot C, Chip 9, SDRAM U59: MAC:0x000029, bank 0, port 2 MSW, exp:0x6492 actual:0x2492
  Slot C, Chip 9, SDRAM U59: MAC:0x00002a, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
  Slot C, Chip 9, SDRAM U59: MAC:0x00002d, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
  -- Reading Bonus Data --
> Slot C, Chip 9: Master Clock from Chip 9 Test Failed!
  -- Reading Full Channel Normal Data --
  -- Reading Bonus Data --
  Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
  TEST  2: Slave  Clock from CHIP 9 ...
  -- Reading Full Channel Normal Data --
  Slot C, Chip 9, SDRAM U59: MAC:0x000000, bank 0, port 2 MSW, exp:0xe739 actual:0xa739
  Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0x739c actual:0x339c
  Slot C, Chip 9, SDRAM U59: MAC:0x000004, bank 0, port 2 MSW, exp:0xce73 actual:0x8e73
  Slot C, Chip 9, SDRAM U59: MAC:0x000005, bank 0, port 2 MSW, exp:0xe733 actual:0xa733
  Slot C, Chip 9, SDRAM U59: MAC:0x000006, bank 0, port 2 MSW, exp:0x7339 actual:0x3339
  Slot C, Chip 9, SDRAM U59: MAC:0x00000a, bank 0, port 2 MSW, exp:0xce73 actual:0x8e73
  Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0xe739 actual:0xa739
  Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0x739c actual:0x339c
  Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0xcce7 actual:0x8ce7
  Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0xce73 actual:0x8e73
  Slot C, Chip 9, SDRAM U59: MAC:0x000011, bank 0, port 2 MSW, exp:0xe739 actual:0xa739
  Slot C, Chip 9, SDRAM U59: MAC:0x000012, bank 0, port 2 MSW, exp:0x739c actual:0x339c
  Slot C, Chip 9, SDRAM U59: MAC:0x000015, bank 0, port 2 MSW, exp:0xce73 actual:0x8e73
  Slot C, Chip 9, SDRAM U59: MAC:0x000016, bank 0, port 2 MSW, exp:0xe733 actual:0xa733
  Slot C, Chip 9, SDRAM U59: MAC:0x000017, bank 0, port 2 MSW, exp:0x7339 actual:0x3339
  Slot C, Chip 9, SDRAM U59: MAC:0x00001b, bank 0, port 2 MSW, exp:0xce73 actual:0x8e73
  Slot C, Chip 9, SDRAM U59: MAC:0x00001c, bank 0, port 2 MSW, exp:0xe739 actual:0xa739
  -- Reading Bonus Data --
> Slot C, Chip 9: Slave  Clock from Chip 9 Test Failed!
  -- Reading Full Channel Normal Data --
  -- Reading Bonus Data --
  Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
  TEST  3: Master Clock from CHIP 8 thru Chip 9 ...
  -- Reading Full Channel Normal Data --
  Slot C, Chip 9, SDRAM U59: MAC:0x000000, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
  Slot C, Chip 9, SDRAM U59: MAC:0x000002, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
  Slot C, Chip 9, SDRAM U59: MAC:0x000003, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
  Slot C, Chip 9, SDRAM U59: MAC:0x000005, bank 0, port 2 MSW, exp:0x6d9b actual:0x2d9b
  Slot C, Chip 9, SDRAM U59: MAC:0x000006, bank 0, port 2 MSW, exp:0xd9b6 actual:0x99b6
  Slot C, Chip 9, SDRAM U59: MAC:0x000009, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
  Slot C, Chip 9, SDRAM U59: MAC:0x00000a, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
  Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
  Slot C, Chip 9, SDRAM U59: MAC:0x00000d, bank 0, port 2 MSW, exp:0xdb66 actual:0x9b66
  Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0x66db actual:0x26db
  Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
  Slot C, Chip 9, SDRAM U59: MAC:0x000011, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
  Slot C, Chip 9, SDRAM U59: MAC:0x000013, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
  Slot C, Chip 9, SDRAM U59: MAC:0x000014, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
  Slot C, Chip 9, SDRAM U59: MAC:0x000016, bank 0, port 2 MSW, exp:0x6d9b actual:0x2d9b
  Slot C, Chip 9, SDRAM U59: MAC:0x000017, bank 0, port 2 MSW, exp:0xd9b6 actual:0x99b6
  Slot C, Chip 9, SDRAM U59: MAC:0x00001a, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
  -- Reading Bonus Data --
> Slot C, Chip 9: Master Clock from Chip 8 thru Chip 9 Test Failed!
  -- Reading Full Channel Normal Data --
  -- Reading Bonus Data --
  Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
  TEST  4: Slave  Clock from CHIP 8 thru Chip 9 ...
  -- Reading Full Channel Normal Data --
  Slot C, Chip 9, SDRAM U59: MAC:0x000002, bank 0, port 2 MSW, exp:0xc631 actual:0x8631
  Slot C, Chip 9, SDRAM U59: MAC:0x000003, bank 0, port 2 MSW, exp:0x6318 actual:0x2318
  Slot C, Chip 9, SDRAM U59: MAC:0x000007, bank 0, port 2 MSW, exp:0xcc63 actual:0x8c63
  Slot C, Chip 9, SDRAM U59: MAC:0x000008, bank 0, port 2 MSW, exp:0xc631 actual:0x8631
  Slot C, Chip 9, SDRAM U59: MAC:0x000009, bank 0, port 2 MSW, exp:0x6318 actual:0x2318
  Slot C, Chip 9, SDRAM U59: MAC:0x00000d, bank 0, port 2 MSW, exp:0xc633 actual:0x8633
  Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0x6331 actual:0x2331
  Slot C, Chip 9, SDRAM U59: MAC:0x000013, bank 0, port 2 MSW, exp:0xc631 actual:0x8631
  Slot C, Chip 9, SDRAM U59: MAC:0x000014, bank 0, port 2 MSW, exp:0x6318 actual:0x2318
  Slot C, Chip 9, SDRAM U59: MAC:0x000018, bank 0, port 2 MSW, exp:0xcc63 actual:0x8c63
  Slot C, Chip 9, SDRAM U59: MAC:0x000019, bank 0, port 2 MSW, exp:0xc631 actual:0x8631
  Slot C, Chip 9, SDRAM U59: MAC:0x00001a, bank 0, port 2 MSW, exp:0x6318 actual:0x2318
  Slot C, Chip 9, SDRAM U59: MAC:0x00001e, bank 0, port 2 MSW, exp:0xc633 actual:0x8633
  Slot C, Chip 9, SDRAM U59: MAC:0x00001f, bank 0, port 2 MSW, exp:0x6331 actual:0x2331
  Slot C, Chip 9, SDRAM U59: MAC:0x000024, bank 0, port 2 MSW, exp:0xc631 actual:0x8631
  Slot C, Chip 9, SDRAM U59: MAC:0x000025, bank 0, port 2 MSW, exp:0x6318 actual:0x2318
  Slot C, Chip 9, SDRAM U59: MAC:0x000029, bank 0, port 2 MSW, exp:0xcc63 actual:0x8c63
  -- Reading Bonus Data --
> Slot C, Chip 9: Slave  Clock from Chip 8 thru Chip 9 Test Failed!
  -- Reading Full Channel Normal Data --
  -- Reading Bonus Data --
  Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
  TEST  5: Psync  Clock from CHIP 8 thru CHIP 9 ...
  -- Reading Full Channel Normal Data --
  Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
  Slot C, Chip 9, SDRAM U59: MAC:0x000002, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
  Slot C, Chip 9, SDRAM U59: MAC:0x000004, bank 0, port 2 MSW, exp:0x6db7 actual:0x2db7
  Slot C, Chip 9, SDRAM U59: MAC:0x000005, bank 0, port 2 MSW, exp:0xdb76 actual:0x9b76
  Slot C, Chip 9, SDRAM U59: MAC:0x000007, bank 0, port 2 MSW, exp:0x76db actual:0x36db
  Slot C, Chip 9, SDRAM U59: MAC:0x000008, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
  Slot C, Chip 9, SDRAM U59: MAC:0x000009, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
  Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
  Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
  Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0x6ddb actual:0x2ddb
  Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0xddb6 actual:0x9db6
  Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
  Slot C, Chip 9, SDRAM U59: MAC:0x000012, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
  Slot C, Chip 9, SDRAM U59: MAC:0x000013, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
  Slot C, Chip 9, SDRAM U59: MAC:0x000015, bank 0, port 2 MSW, exp:0x6db7 actual:0x2db7
  Slot C, Chip 9, SDRAM U59: MAC:0x000016, bank 0, port 2 MSW, exp:0xdb76 actual:0x9b76
  Slot C, Chip 9, SDRAM U59: MAC:0x000018, bank 0, port 2 MSW, exp:0x76db actual:0x36db
  -- Reading Bonus Data --
> Slot C, Chip 9: Slave  Clock from Chip 9 thru Chip 8 Test Failed!
  Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
  TEST  6: Master Clock from CHIP 8 ...
  -- Reading Full Channel Normal Data --
  -- Reading Bonus Data --
  TEST  7: Slave  Clock from CHIP 8 ...
  -- Reading Full Channel Normal Data --
  -- Reading Bonus Data --
  TEST  8: Master Clock from CHIP 9 thru CHIP 8 ...
  -- Reading Full Channel Normal Data --
  -- Reading Bonus Data --
  TEST  9: Slave  Clock from CHIP 9 thru CHIP 8 ...
  -- Reading Full Channel Normal Data --
  -- Reading Bonus Data --
  TEST 10: Psync  Clock from CHIP 9 thru CHIP 8 ...
  -- Reading Full Channel Normal Data --
  -- Reading Bonus Data --
  TEST 11: Poststore Counter Test ...
Mod   C: TEST FAILED       # "clksTest" (1, 1, -1)
 

Offline nikodem

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Re: Series defect on agilent 167xx boards?
« Reply #67 on: January 29, 2021, 09:51:03 pm »
Which leg did you lift? One of the data lines?

I'll try to poke around the board tommorow, to check for broken traces (again), wish me luck
 

Offline MarkL

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Re: Series defect on agilent 167xx boards?
« Reply #68 on: January 29, 2021, 10:13:43 pm »
Which leg did you lift? One of the data lines?
Says it at the top of the notes.
 

Offline nikodem

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Re: Series defect on agilent 167xx boards?
« Reply #69 on: February 10, 2021, 06:05:53 pm »
I have locate a single trace, that was broken between the acqusition ASIC and the FPGA glue logic  :clap: that damn f...failed trace was hidden UNDER OVERLAY, uh. It was looking kinda clocky, as it was length matched. Now I see the following result of anlyBusTest:

Code: [Select]
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=00000002, act=00000000
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFFE, act=FFFFFFFC
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFFB, act=FFFFFFF9
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFF7, act=FFFFFFF5
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFEF, act=FFFFFFED
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFDF, act=FFFFFFDD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFBF, act=FFFFFFBD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFF7F, act=FFFFFF7D
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFEFF, act=FFFFFEFD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFDFF, act=FFFFFDFD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFBFF, act=FFFFFBFD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFF7FF, act=FFFFF7FD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFEFFF, act=FFFFEFFD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFDFFF, act=FFFFDFFD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFBFFF, act=FFFFBFFD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFF7FFF, act=FFFF7FFD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFEFFFF, act=FFFEFFFD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFDFFFF, act=FFFDFFFD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFBFFFF, act=FFFBFFFD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFF7FFFF, act=FFF7FFFD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFEFFFFF, act=FFEFFFFD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFDFFFFF, act=FFDFFFFD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFBFFFFF, act=FFBFFFFD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FF7FFFFF, act=FF7FFFFD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FEFFFFFF, act=FEFFFFFD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FDFFFFFF, act=FDFFFFFD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FBFFFFFF, act=FBFFFFFD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=F7FFFFFF, act=F7FFFFFD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=EFFFFFFF, act=EFFFFFFD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=DFFFFFFF, act=DFFFFFFD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=BFFFFFFF, act=BFFFFFFD
  Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=7FFFFFFF, act=7FFFFFFD
  Slot A, Analysis Chip Data Bit Error, chip 9, port 2, bits=00000002
Mod   A: TEST FAILED       # "anlyBusTest" (3, 3, -1)

Which is much much better, because the RAM now is working and only a single bit (DQ1 of the lower chip I presume) is faulty. The clksTest seems to confirm that:



I will try to investigate the U50, especially stuff that is connected to the DQ1 (4th pin). Or maybe the failure is somwhere else? because if the DQ1 would be e.g. not connected, then as you shown I should get much more errors. Right?

Thanks all for the support! and keep fingers crossed.

// EDIT:

Found another trace between ASIC and FPGA, that has been corroded in an invisible way... It wasn't even under those sliders with corrosive glue (only next to it). Some serious scraping was needed, to find, where it was broken (under the solder mask). After soldering it together, the board passed all the tests!  :-+

I need to run some more tests now (the tests were just triffered from the GUI, didn't had time for pv) but I hope that it is repaired!

Thank you all for your invaluable help and assistance.
« Last Edit: February 11, 2021, 08:50:56 am by nikodem »
 

Offline MarkL

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Re: Series defect on agilent 167xx boards?
« Reply #70 on: February 11, 2021, 10:19:38 pm »
I have locate a single trace, that was broken between the acqusition ASIC and the FPGA glue logic  :clap: that damn f...failed trace was hidden UNDER OVERLAY, uh. It was looking kinda clocky, as it was length matched.
This is why I cautioned you to methodically test end-to-end by probing the vias.  Corrosion damage is sometimes difficult to see.

Quote
Now I see the following result of anlyBusTest:
...
See attached photo for the trace that carries anlyBus bit 00000002.  I have indicated the two endpoint vias and the probe pad in the middle.  Again, a common spot for corrosion breaks is around the probe pads, but can occur anywhere.
 

Offline MarkL

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Re: Series defect on agilent 167xx boards?
« Reply #71 on: February 23, 2021, 01:34:48 am »
Glad you got it working, and you're welcome!

I didn't see your EDIT to your post that you got it working until after I posted.  (Actually, not until today.)

Which trace did you fix?  Was it the one I showed in the photo or something else?  Did your additional tests succeed also?
 

Offline Hamster

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Re: Series defect on agilent 167xx boards?
« Reply #72 on: March 29, 2021, 03:51:22 am »
seems i got the runner failure delima..

i have 3 dead 16751A
i have 2 dead 16750A
i have 1 dead 16534A

working: 2 16534A
working: 2 16715A
working: 1 16716A

i have a 1680A now, so probably not going to spend to much on these.. probably going to scrap.

i will keep the 715/716A ( after removing the runners and cleaning ) , its funny how they were completly caked in dust.. seems the dust saved them. all cards with issues look like large xilinix chips with silver tops have started to "corrode/rust" seems these boards all have a limited lifespan.

Arcade Board Repair Guru.  [ twitch: HammysHangout , youTube: Hammy Builds ]
 

Offline MarkL

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Re: Series defect on agilent 167xx boards?
« Reply #73 on: March 29, 2021, 04:05:19 pm »
I've had corrosion/rust on the Xilinx tops too.  No metal on these boards seems to be safe.

The 16534A is the most repairable of the bunch.  I wouldn't scrap that.  Out of 6 or 7 broken 16534A cards that I had, I was able to fix all of them.  Most had corroded traces and visibly damaged components which were easily repaired.
 

Offline Hamster

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Re: Series defect on agilent 167xx boards?
« Reply #74 on: March 30, 2021, 04:13:52 am »
Yep, Fixed the 16534.

I was able to fix a 16751A that had just about every test failed, now down to 3:

Analyzer Chip Memory Bus Test
System Clocks ( Master/Slave/Psync) Test 
Analyzer Memory Bus SU/H Measure

Any suggestions on best method to "Safely" remove the plastic runners without damaging traces?  i pulled up two pads removing one.. but they were just pogo pin test pads, so was able to repair without issue.



Arcade Board Repair Guru.  [ twitch: HammysHangout , youTube: Hammy Builds ]
 


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