Electronics > Repair
Series defect on agilent 167xx boards?
MarkL:
Also, it's worth noting that if one test fails, I've found that you should concentrate on fixing that one first. Subsequent failures are usually a consequence of the first failure reported.
nikodem:
OK, so I wanted to update the topic. I've cleaned the whole board, and tested it again, this time using pv. It showed the same failed tests. I've found two obviously broken traces, that from the location look like there are connecting the DAC with the comparators (judging from the location etc).
After fixing the traces I've got the following result from pv:
--- Code: ---Mod A : (0x34) 16750A Logic Analyzer (Master)
Summary Test Name #Tests #Fails
------------------------------------------------------
passed cpldRegTest 2 0
passed testLoadFPGA 2 0
passed fpgaRegTest 2 0
passed dataBusTest 2 0
passed addrBusTest 2 0
passed hwMemoryCellTest 2 0
passed unloadTest 2 0
passed dmaTest 2 0
passed sleepTest 2 0
passed searchTest 2 0
passed chipRegTest 1 0
FAILED anlyBusTest 1 1
FAILED clksTest 1 1
FAILED measAnlyBusTiming 1 1
passed bpClkTest 1 0
passed cmpTest 3 0
passed icrTest 1 0
passed flagTest 1 0
passed armTest 1 0
passed calTest 1 0
passed zoomDataTest 1 0
passed zoomMasterTest 1 0
passed fisoRedundancyTest 1 0
FAILED zoomAcqTest 17 3
passed zoomChipSelTest 5 0
--- End code ---
So it seems to have fixed the cmpTest and zoomChipSelTest, but now the zoomAcqTest fails from time to time. After reseting the pv I've rerun the test 20 times and it was fine :-// it also passed with flying colors when umaking the self-test on the device itself.
So now I have to worry only about the anlyBusTest, clksTest and measAnlyBusTiming. Does anyone has any closer information regarding those?
MarkL:
Please read Keith's and my post above about turning on debugging output for pv. Here's another thread that talks about pv:
https://www.eevblog.com/forum/repair/logic-analyzer-boards-repair/msg2235390/#msg2235390
There is a service guide that describes each of the tests performed. These descriptions can provide additional clues on where to look for problems when combined with the debugging output:
http://literature.cdn.keysight.com/litweb/pdf/16750-97003.pdf
You should also read the whole Theory of Operation chapter. There's very little service information out there about these cards, so you need to fully absorb everything that you can.
nikodem:
OK, I've did some debugging and serious thinking :-/O it seems, that one of the memory chips is broken(ish). My module is failing the following tests:
* anlyBusTest - Analyzer Chip Memory Bus Test
* clksTest - System Clocks (Master/Slave/Psync) Test
* measAnlyBusTiming - Analyzer Memory Bus SU/H Measure[/il]
All of them use chip memory! anlyBusTest checks it directly using a walking 1 pattern and reports:
--- Code: ---Slot A, Analysis Chip Data Bit Failed, chip 9, port 2
--- End code ---
for all the bits (0xFFFFFFFF) of the chip 9, port 2 of the memory. The module has 34 memory chips (48LC4M16A2 - 1Mx16x4 SDRAMs) organized in 32-bit memory. Do I assume correctly, that this means that one of the memory chips is damaged or lost its connection to the Virtex FPGAs? Do you have any idea how to check which one? :-DMM
Regards :) and thank you for your help.
MarkL:
In the pv output "Chip 8" and "Chip 9" refer to the acquisition ASICs.
Please post (attach) your output from pv with "d r=9" turned on so we can have some context. At the moment, the output from anlyBusTest and clksTest will do.
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