Electronics > Repair
Series defect on agilent 167xx boards?
<< < (13/50) > >>
MarkL:
CLK, CKE, and CS# are all connected to one side of various 10k resistors on the top, and also to one side of the 33R horizontal resistor packs on the bottom.

It seems DQMH and DQML are connected together on all the chips in the group (U60, U59, U47, U51, U60, U90, U89, U87, U86), and go to one side of a blue 38R resistor on top.

It's your board, but I would not start swapping chips until I have a reason to believe it's the chip.  Plus, I'm more likely to believe it's one chip that has gone bad and not both.

I would try the live probing first to see if the U50/U59 are getting the same anlyBusTest test signals that another working pair are seeing, like U23/U30.  Note that the two halves of the board are practically identical copies of each other, at least for the data acquisition piece, and you can use this to your advantage for comparison purposes when you have something failing only on one half.

EDIT:  A further thought on this...  You should note that the memory chips all passed previous read/write tests without error.  The problem appears to be when the acquisition chips are in charge of writing to the memory.  The previous tests, I believe, are done through the bus interface (Altera) FPGAs.
nikodem:

--- Quote from: MarkL on January 25, 2021, 12:37:23 am ---A further thought on this...  You should note that the memory chips all passed previous read/write tests without error.  The problem appears to be when the acquisition chips are in charge of writing to the memory.  The previous tests, I believe, are done through the bus interface (Altera) FPGAs.
--- End quote ---

From what I understand this is the first test involving memory. All further also fail.
MarkL:

--- Quote from: nikodem on January 25, 2021, 04:29:22 pm ---
--- Quote from: MarkL on January 25, 2021, 12:37:23 am ---A further thought on this...  You should note that the memory chips all passed previous read/write tests without error.  The problem appears to be when the acquisition chips are in charge of writing to the memory.  The previous tests, I believe, are done through the bus interface (Altera) FPGAs.
--- End quote ---

From what I understand this is the first test involving memory. All further also fail.

--- End quote ---
No.  The following tests also involve the acquisition memory and are performed before the anlyBusTest:

  dataBusTest
  addrBusTest
  hwMemoryCellTest
  unloadTest
  dmaTest
  sleepTest

You previously reported that all of these passed.
nikodem:
Indeed you are right. Is there any more documentation showing what exactly is checked by which test? On a tad lower level, so I can compare it with the hardware.

The memory ICs seem to be connected only to the Virtex FPGAs, and the lines seem to be fine. So now it's tim to check what is going on between the ASICs and the big FPGA, that controlls the offending memory chip...  :-DMM
MarkL:

--- Quote from: nikodem on January 26, 2021, 05:59:54 pm ---Indeed you are right. Is there any more documentation showing what exactly is checked by which test? On a tad lower level, so I can compare it with the hardware.

--- End quote ---
Other than what's stated in the service guide, I'm not aware of anything.  It's clearly stated that the acquisition memory is thoroughly tested via those tests.

If you're ever in doubt, you could always lift a leg on a working memory chip and observe which tests detect it.


--- Quote ---The memory ICs seem to be connected only to the Virtex FPGAs, and the lines seem to be fine. So now it's tim to check what is going on between the ASICs and the big FPGA, that controlls the offending memory chip...  :-DMM

--- End quote ---
I have a 16750A with one FPGA and one ASIC removed, and that is correct the memory lines only go to the FPGA.

The 16715A/16716A/16717A cards (and maybe others) have a very similar, if not identical, acquisition ASIC footprint and PCB layout as the 16750A.  And in those cards, the ASIC drives the memory directly without intervening FPGAs.  Another thing is that even though the 16750A cards have more total memory bits, the number of physical memory chips is the same (34).

My suspicion is that Agilent did not want to re-spin (or maybe make very minimal changes to) the acquisition ASIC for cost reasons and instead opted to create an adaption layer to take the memory control signals from the existing ASIC and control a larger pool of memory.

So, it may be that there is a direct correlation for the control lines to U50/U59 to one or more signals coming out of the acquisition ASIC, U45.

The acquisition ASICs in the 16715A/16A/17A do have a different part number than the 16750A, but it's also a different manufacturer ("LSI L2B1075 HP 1821-3936" vs. "Agilent L2A1509").  They may have some differences internally, but I'm looking at the footprint and how the PCB traces are arranged.


EDIT:  After looking up "L2A1509", it appears that's also made by LSI.  So the manufacturer is the same.  Minor point.
Navigation
Message Index
Next page
Previous page
There was an error while thanking
Thanking...

Go to full version
Powered by SMFPacks Advanced Attachments Uploader Mod