I have returned to this project and need to consolidate parts of this from another thread (
https://www.eevblog.com/forum/repair/tektronix-dpo4054-stucked-at-tektronix-splash-screen/msg3459646/#msg3459646) for my own documentation/sanity. The key points are below.
The oscillator at Y650 is 27MHz and looks good, steady through the whole process.
There are two LTC3728 and one LTC3729 that all look ok. The PGOOD signal on all of them isn't pulled down.
The EEPROM at U431 has steady power but no activity on the one address line that isn't directly tied to ground. There are only 2 pulses low on the SDA and one on the SCL upon boot, exact same results every time.
All oscillators on both sides are present and stable. The CPU does have an integrated PLL.
I checked every pin imaginable from the vias under the CPU BGA. The only suspect was clkEn which enables the RAM clock. It is steady at 2.2v instead of the documented 2.5v in the CPU datasheet. However, I believe that is still within SSTL 2 specs.
I confirmed the CPU bootstrap is configured to gather boot configuration from the 16 bytes on the I2C EEPROM. I believe that is telling the CPU to get the bootloader from the 4MB flash chip at U822. The CE and OE pins between the CPU and U822 start enabled and then go high at the same time the boot log stops. I think bootloader instructions are interrupted because of this. I just don't know why the CPU is doing this.
I confirmed the DDR termination regulator is at U650 and is behaving as specified in the datasheet.
Sadly, I have ruled out voltages, DDR termination and oscillators.
U822 is a Am29LV040B PLCC. Does anyone have a dump of this chip? This MSO4104(non-B) has the same version header as others have posted from different versions of the 4000. "U-Boot 1.1.4 (Jan 8 2007 - 11:12:14) Tektronix, Inc. V1.06". I'm not sure if that means it's universal and interchangeable but I also found this same version digging through the downloadable FW update from Tek. Maybe I'll desolder and compare the two.
IR Cam shows no overheating either side of board.
After desoldering and dumping the existing code on U822 I can see it contains more than just the bootloader. I compared it to the bootloader.img obtained via 'binwalk -e' of the latest firmware from the Tektronix website. Some fancy dd work on this might merge them, overwriting the bootloader portion to make things work but I would rather receive a U822 dump from someone else in the community so I know it is a functional copy. The results are below.
binwalk of U822 dump (524KB)
DECIMAL HEXADECIMAL DESCRIPTION
--------------------------------------------------------------------------------
295 0x127 Unix path: /vol/ibunix01/r66tools/r66tools/mvserve/filesys
1370 0x55A U-Boot version string, "U-Boot 1.0.0 (Sep 8 2006 - 08:50:07) Tektronix, Inc. V1.02"
262144 0x40000 uImage header, header size: 64 bytes, header CRC: 0x552D426F, created: 2029-04-03 03:29:53, image size: 774975028 bytes, Data Address: 0x20284A61, Entry Point: 0x6E202038, data CRC: 0x20323030, image name: "11:12:14) Tektronix, Inc. V1.06"
262148 0x40004 U-Boot version string, "U-Boot 1.1.4 (Jan 8 2007 - 11:12:14) Tektronix, Inc. V1.06"
381312 0x5D180 CRC32 polynomial table, big endian
386984 0x5E7A8 U-Boot version string, "U-Boot 1.1.4"
414044 0x6515C Unix path: /vol/ibunix03/r66tools/r66tools/mvserve/filesys
binwalk of bootloader.img from Tek (262KB)
DECIMAL HEXADECIMAL DESCRIPTION
--------------------------------------------------------------------------------
0 0x0 uImage header, header size: 64 bytes, header CRC: 0x552D426F, created: 2029-04-03 03:29:53, image size: 774975028 bytes, Data Address: 0x20284A61, Entry Point: 0x6E202038, data CRC: 0x20323030, image name: "11:12:14) Tektronix, Inc. V1.06"
4 0x4 U-Boot version string, "U-Boot 1.1.4 (Jan 8 2007 - 11:12:14) Tektronix, Inc. V1.06"
119168 0x1D180 CRC32 polynomial table, big endian
124840 0x1E7A8 U-Boot version string, "U-Boot 1.1.4"
151900 0x2515C Unix path: /vol/ibunix03/r66tools/r66tools/mvserve/filesys
assuming the flash chip is ok, I think the cpu stalls when she wants to communicate with a peripheral device/chip and perhaps does not get the right response/acknowledge. At this early stage I think it is more likely to be a device on the PCI bus
PCI: Bus Dev VenId DevId Class Int
00 13 10b5 9056 0680 18
00 15 1002 4c59 0300 17
the first device is the PCI Bus Master chip made by PLX (PCI9056) and the second device in the list is the ATI Mobility Radeon graphics processor
but how to troubleshoot their connection? is beyond me...

vcc and clock are good on the PCI9056 at U560 but the IDSEL(thanks m k) line is stuck low. The datasheet of this chip and the 440EP CPU show their IDSEL pins as input. Anyone know the source?
BTW: I programmed the flash with the downloaded and extracted bootloader.img just to see what would happen but it wouldn't even provide a boot log, completely dead. I reprogrammed it with the original code and it's back to the previous behavior. I thought I would add this here just in case someone is playing with firmware in the future. I suppose a merge of that img file with the original code might work but I believe you all are correct; if it was damaged I wouldn't get much useful info out of it.
Good, or bad, now it's at least known that something excact is clearly something it shouldn't.
Is it a cause is another thing.
I don't know the correct PCI naming policies and the whole PCI hierarchy has always been a bit messy.
A controller can also be PCI to PCI and then another PCI controller is what you think is the first one.
Did I read it right that this 440EP can also be a PCI controller, so the 2nd in PCI line.
One construction model is CPU-PLB-bridge-PCI-controller/bridge-stuff.
There is also a method called PCI boot, where PCI memory can be accessed without configuration, it can obviously be misused for what ever purposes.
In this case it's quite possible that PCI something is predefined.
Since the system knows that some parts are there, or should be, always, it can expect them.
So if PCI 9056 is not first its missing ID request can be fine, but since that other boot log has it as first, one must follow that.
Though it doesn't exclude that there isn't something else before that but would it be completely silent in the log.
For the interrupt,
if it's PCI and not configured it should be ingnored.
One method for IDSEL is to decode one address line for each PCI connection IDSEL.
PPC440EPx-GRx manual says that device 1 is AD11.
If those addresses are used elsewhere there must be a chip with enable in between somewhere.