Electronics > Repair
Tektronix DPO7104 repairs
<< < (6/9) > >>
pasta2018:
With another DPO7054 operating system, I can now access the oscilloscope test interface. However, there are some errors, registers 224 and acquisition error
iAleks:
Download here your console.txt and diag.txt from C:\TekScope\calibration
pasta2018:
it seems mainly point to U200,but I havn't find this chip on acquisition board.


--- Code: ---Fri Dec 20 23:06:08 2024: DIAGNOSTIC EXECUTION starting ... Pu=2 T=-127C
Test "111" - Processor-->Memory-->DRAMWalk1 started
     Test execution time 2.7937e-006 sec
Test "112" - Processor-->Memory-->DRAMCell started
     Test execution time 0.025139 sec
Test "113" - Processor-->Memory-->DRAMMarch  started
     Test execution time 0.001479 sec
Test "114" - Processor-->Memory-->DRAMCal  started
     Test execution time 1.9556e-006 sec
Test "211" - Registers-->PCI-->MIA started
     Test execution time 0.0001422 sec
Test "221" - Registers-->Acquisition-->ACL started
     Test execution time 0.00068221 sec
Test "222" - Registers-->Acquisition-->PLL started
     Test execution time 0.02519 sec
Test "223" - Registers-->Acquisition-->Preamp started
     Test execution time 0.31132 sec
Test "224" - Registers-->Acquisition-->TrkHld started

DataLineTstStepFail- U200(HFD201[0])/SPARE_0+0x000 exp/act 0x1/0x0

DataLineTstStepFail- U200(HFD201[0])/SPARE_0+0x000 exp/act 0xfe/0x0

DataLineTstStepFail- U200(HFD201[0])/SPARE_0+0x000 exp/act 0x2/0x0

DataLineTstStepFail- U200(HFD201[0])/SPARE_0+0x000 exp/act 0xfd/0x0

DataLineTstStepFail- U200(HFD201[0])/SPARE_0+0x000 exp/act 0x4/0x0

DataLineTstStepFail- U200(HFD201[0])/SPARE_0+0x000 exp/act 0xfb/0x0

DataLineTstStepFail- U200(HFD201[0])/SPARE_0+0x000 exp/act 0x8/0x0

DataLineTstStepFail- U200(HFD201[0])/SPARE_0+0x000 exp/act 0xf7/0x0

DataLineTstStepFail- U200(HFD201[0])/SPARE_0+0x000 exp/act 0x10/0x0

DataLineTstStepFail- U200(HFD201[0])/SPARE_0+0x000 exp/act 0xef/0x0

DataLineTstStepFail- U200(HFD201[0])/SPARE_0+0x000 exp/act 0x20/0x0

DataLineTstStepFail- U200(HFD201[0])/SPARE_0+0x000 exp/act 0xdf/0x0

DataLineTstStepFail- U200(HFD201[0])/SPARE_0+0x000 exp/act 0x40/0x0

DataLineTstStepFail- U200(HFD201[0])/SPARE_0+0x000 exp/act 0xbf/0x0

DataLineTstStepFail- U200(HFD201[0])/SPARE_0+0x000 exp/act 0x80/0x0

DataLineTstStepFail- U200(HFD201[0])/SPARE_0+0x000 exp/act 0x7f/0x0

DataLineTstStepFail- U200(HFD201[0])/SPARE_0+0x000 exp/act 0xff/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x000 exp/act 0x1fe/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x000 exp/act 0x1fd/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x000 exp/act 0x1fb/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x000 exp/act 0x8/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x000 exp/act 0x1f7/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x000 exp/act 0x10/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x000 exp/act 0x1ef/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x000 exp/act 0x20/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x000 exp/act 0x1df/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x000 exp/act 0x40/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x000 exp/act 0x1bf/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x000 exp/act 0x80/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x000 exp/act 0x17f/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x000 exp/act 0x100/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x000 exp/act 0xff/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x000 exp/act 0x1ff/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x001 exp/act 0x1/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x001 exp/act 0x1fe/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x001 exp/act 0x2/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x001 exp/act 0x1fd/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x001 exp/act 0x4/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x001 exp/act 0x1fb/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x001 exp/act 0x8/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x001 exp/act 0x1f7/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x001 exp/act 0x10/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x001 exp/act 0x1ef/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x001 exp/act 0x20/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x001 exp/act 0x1df/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x001 exp/act 0x40/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x001 exp/act 0x1bf/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x001 exp/act 0x80/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x001 exp/act 0x17f/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x001 exp/act 0x100/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x001 exp/act 0xff/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x001 exp/act 0x1ff/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x002 exp/act 0x1/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x002 exp/act 0x1fe/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x002 exp/act 0x2/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x002 exp/act 0x1fd/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x002 exp/act 0x4/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x002 exp/act 0x1fb/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x002 exp/act 0x8/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x002 exp/act 0x1f7/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x002 exp/act 0x10/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x002 exp/act 0x1ef/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x002 exp/act 0x20/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x002 exp/act 0x1df/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x002 exp/act 0x40/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x002 exp/act 0x1bf/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x002 exp/act 0x80/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x002 exp/act 0x17f/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x002 exp/act 0x100/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x002 exp/act 0xff/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x002 exp/act 0x1ff/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x003 exp/act 0x1/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x003 exp/act 0x1fe/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x003 exp/act 0x2/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x003 exp/act 0x1fd/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x003 exp/act 0x4/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x003 exp/act 0x1fb/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x003 exp/act 0x8/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x003 exp/act 0x1f7/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x003 exp/act 0x10/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x003 exp/act 0x1ef/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x003 exp/act 0x20/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x003 exp/act 0x1df/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x003 exp/act 0x40/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x003 exp/act 0x1bf/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x003 exp/act 0x80/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x003 exp/act 0x17f/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x003 exp/act 0x100/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x003 exp/act 0xff/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ+0x003 exp/act 0x1ff/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ_A+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ_A+0x000 exp/act 0x1fe/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ_A+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ_A+0x000 exp/act 0x1fd/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ_A+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ_A+0x000 exp/act 0x1fb/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ_A+0x000 exp/act 0x8/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ_A+0x000 exp/act 0x1f7/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ_A+0x000 exp/act 0x10/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ_A+0x000 exp/act 0x1ef/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ_A+0x000 exp/act 0x20/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ_A+0x000 exp/act 0x1df/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ_A+0x000 exp/act 0x40/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ_A+0x000 exp/act 0x1bf/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ_A+0x000 exp/act 0x80/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ_A+0x000 exp/act 0x17f/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ_A+0x000 exp/act 0x100/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ_A+0x000 exp/act 0xff/0x0

Wlk1HWMismatch (0x11) - U200(HFD201[0])/HFADJ_A+0x000 exp/act 0x1ff/0x0

Wlk1HWMismatch (0x12) - U200(HFD201[0])/HFADJ_B+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x12) - U200(HFD201[0])/HFADJ_B+0x000 exp/act 0x1fe/0x0

Wlk1HWMismatch (0x12) - U200(HFD201[0])/HFADJ_B+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x12) - U200(HFD201[0])/HFADJ_B+0x000 exp/act 0x1fd/0x0

Wlk1HWMismatch (0x12) - U200(HFD201[0])/HFADJ_B+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x12) - U200(HFD201[0])/HFADJ_B+0x000 exp/act 0x1fb/0x0

Wlk1HWMismatch (0x12) - U200(HFD201[0])/HFADJ_B+0x000 exp/act 0x8/0x0

Wlk1HWMismatch (0x12) - U200(HFD201[0])/HFADJ_B+0x000 exp/act 0x1f7/0x0

Wlk1HWMismatch (0x12) - U200(HFD201[0])/HFADJ_B+0x000 exp/act 0x10/0x0

Wlk1HWMismatch (0x12) - U200(HFD201[0])/HFADJ_B+0x000 exp/act 0x1ef/0x0

Wlk1HWMismatch (0x12) - U200(HFD201[0])/HFADJ_B+0x000 exp/act 0x20/0x0

Wlk1HWMismatch (0x12) - U200(HFD201[0])/HFADJ_B+0x000 exp/act 0x1df/0x0

Wlk1HWMismatch (0x12) - U200(HFD201[0])/HFADJ_B+0x000 exp/act 0x40/0x0

Wlk1HWMismatch (0x12) - U200(HFD201[0])/HFADJ_B+0x000 exp/act 0x1bf/0x0

Wlk1HWMismatch (0x12) - U200(HFD201[0])/HFADJ_B+0x000 exp/act 0x80/0x0

Wlk1HWMismatch (0x12) - U200(HFD201[0])/HFADJ_B+0x000 exp/act 0x17f/0x0

Wlk1HWMismatch (0x12) - U200(HFD201[0])/HFADJ_B+0x000 exp/act 0x100/0x0

Wlk1HWMismatch (0x12) - U200(HFD201[0])/HFADJ_B+0x000 exp/act 0xff/0x0

Wlk1HWMismatch (0x12) - U200(HFD201[0])/HFADJ_B+0x000 exp/act 0x1ff/0x0

Wlk1HWMismatch (0x13) - U200(HFD201[0])/HFADJ_C+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x13) - U200(HFD201[0])/HFADJ_C+0x000 exp/act 0x1fe/0x0

Wlk1HWMismatch (0x13) - U200(HFD201[0])/HFADJ_C+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x13) - U200(HFD201[0])/HFADJ_C+0x000 exp/act 0x1fd/0x0

Wlk1HWMismatch (0x13) - U200(HFD201[0])/HFADJ_C+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x13) - U200(HFD201[0])/HFADJ_C+0x000 exp/act 0x1fb/0x0

Wlk1HWMismatch (0x13) - U200(HFD201[0])/HFADJ_C+0x000 exp/act 0x8/0x0

Wlk1HWMismatch (0x13) - U200(HFD201[0])/HFADJ_C+0x000 exp/act 0x1f7/0x0

Wlk1HWMismatch (0x13) - U200(HFD201[0])/HFADJ_C+0x000 exp/act 0x10/0x0

Wlk1HWMismatch (0x13) - U200(HFD201[0])/HFADJ_C+0x000 exp/act 0x1ef/0x0

Wlk1HWMismatch (0x13) - U200(HFD201[0])/HFADJ_C+0x000 exp/act 0x20/0x0

Wlk1HWMismatch (0x13) - U200(HFD201[0])/HFADJ_C+0x000 exp/act 0x1df/0x0

Wlk1HWMismatch (0x13) - U200(HFD201[0])/HFADJ_C+0x000 exp/act 0x40/0x0

Wlk1HWMismatch (0x13) - U200(HFD201[0])/HFADJ_C+0x000 exp/act 0x1bf/0x0

Wlk1HWMismatch (0x13) - U200(HFD201[0])/HFADJ_C+0x000 exp/act 0x80/0x0

Wlk1HWMismatch (0x13) - U200(HFD201[0])/HFADJ_C+0x000 exp/act 0x17f/0x0

Wlk1HWMismatch (0x13) - U200(HFD201[0])/HFADJ_C+0x000 exp/act 0x100/0x0

Wlk1HWMismatch (0x13) - U200(HFD201[0])/HFADJ_C+0x000 exp/act 0xff/0x0

Wlk1HWMismatch (0x13) - U200(HFD201[0])/HFADJ_C+0x000 exp/act 0x1ff/0x0

Wlk1HWMismatch (0x14) - U200(HFD201[0])/HFADJ_D+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x14) - U200(HFD201[0])/HFADJ_D+0x000 exp/act 0x1fe/0x0

Wlk1HWMismatch (0x14) - U200(HFD201[0])/HFADJ_D+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x14) - U200(HFD201[0])/HFADJ_D+0x000 exp/act 0x1fd/0x0

Wlk1HWMismatch (0x14) - U200(HFD201[0])/HFADJ_D+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x14) - U200(HFD201[0])/HFADJ_D+0x000 exp/act 0x1fb/0x0

Wlk1HWMismatch (0x14) - U200(HFD201[0])/HFADJ_D+0x000 exp/act 0x8/0x0

Wlk1HWMismatch (0x14) - U200(HFD201[0])/HFADJ_D+0x000 exp/act 0x1f7/0x0

Wlk1HWMismatch (0x14) - U200(HFD201[0])/HFADJ_D+0x000 exp/act 0x10/0x0

Wlk1HWMismatch (0x14) - U200(HFD201[0])/HFADJ_D+0x000 exp/act 0x1ef/0x0

Wlk1HWMismatch (0x14) - U200(HFD201[0])/HFADJ_D+0x000 exp/act 0x20/0x0

Wlk1HWMismatch (0x14) - U200(HFD201[0])/HFADJ_D+0x000 exp/act 0x1df/0x0

Wlk1HWMismatch (0x14) - U200(HFD201[0])/HFADJ_D+0x000 exp/act 0x40/0x0

Wlk1HWMismatch (0x14) - U200(HFD201[0])/HFADJ_D+0x000 exp/act 0x1bf/0x0

Wlk1HWMismatch (0x14) - U200(HFD201[0])/HFADJ_D+0x000 exp/act 0x80/0x0

Wlk1HWMismatch (0x14) - U200(HFD201[0])/HFADJ_D+0x000 exp/act 0x17f/0x0

Wlk1HWMismatch (0x14) - U200(HFD201[0])/HFADJ_D+0x000 exp/act 0x100/0x0

Wlk1HWMismatch (0x14) - U200(HFD201[0])/HFADJ_D+0x000 exp/act 0xff/0x0

Wlk1HWMismatch (0x14) - U200(HFD201[0])/HFADJ_D+0x000 exp/act 0x1ff/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/IN_MUX_SELECT_A+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/IN_MUX_SELECT_A+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/IN_MUX_SELECT_A+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/IN_MUX_SELECT_A+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/IN_MUX_SELECT_A+0x000 exp/act 0x3/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/IN_MUX_SELECT_B+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/IN_MUX_SELECT_B+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/IN_MUX_SELECT_B+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/IN_MUX_SELECT_B+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/IN_MUX_SELECT_B+0x000 exp/act 0x3/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/IN_MUX_SELECT_C+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/IN_MUX_SELECT_C+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/IN_MUX_SELECT_C+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/IN_MUX_SELECT_C+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/IN_MUX_SELECT_C+0x000 exp/act 0x3/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/IN_MUX_SELECT_D+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/IN_MUX_SELECT_D+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/IN_MUX_SELECT_D+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/IN_MUX_SELECT_D+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/IN_MUX_SELECT_D+0x000 exp/act 0x3/0x0

Wlk1HWMismatch (0x10) - U200(HFD201[0])/LP_SEL_A+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x10) - U200(HFD201[0])/LP_SEL_A+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x10) - U200(HFD201[0])/LP_SEL_B+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x10) - U200(HFD201[0])/LP_SEL_B+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x10) - U200(HFD201[0])/LP_SEL_C+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x10) - U200(HFD201[0])/LP_SEL_C+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x10) - U200(HFD201[0])/LP_SEL_D+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x10) - U200(HFD201[0])/LP_SEL_D+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL+0x000 exp/act 0x3fe/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL+0x000 exp/act 0x3fd/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL+0x000 exp/act 0x3fb/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL+0x000 exp/act 0x8/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL+0x000 exp/act 0x3f7/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL+0x000 exp/act 0x10/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL+0x000 exp/act 0x3ef/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL+0x000 exp/act 0x20/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL+0x000 exp/act 0x3df/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL+0x000 exp/act 0x40/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL+0x000 exp/act 0x3bf/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL+0x000 exp/act 0x80/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL+0x000 exp/act 0x37f/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL+0x000 exp/act 0x100/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL+0x000 exp/act 0x2ff/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL+0x000 exp/act 0x200/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL+0x000 exp/act 0x1ff/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL+0x000 exp/act 0x3ff/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_DEBUG+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_DEBUG+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_DEC+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_DEC+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_DEC+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_DEC+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_DEC+0x000 exp/act 0x3/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_DIV+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_DIV+0x000 exp/act 0xe/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_DIV+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_DIV+0x000 exp/act 0xd/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_DIV+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_DIV+0x000 exp/act 0xb/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_DIV+0x000 exp/act 0x8/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_DIV+0x000 exp/act 0x7/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_DIV+0x000 exp/act 0xf/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_EN+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_EN+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_SEL+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_SEL+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_SEL+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_SEL+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x71) - U200(HFD201[0])/SD_ADC_CTRL_SEL+0x000 exp/act 0x3/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0xffe/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0xffd/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0xffb/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0x8/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0xff7/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0x10/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0xfef/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0x20/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0xfdf/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0x40/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0xfbf/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0x80/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0xf7f/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0x100/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0xeff/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0x200/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0xdff/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0x400/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0xbff/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0x800/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0x7ff/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SIG_MUX_SELECT+0x000 exp/act 0xfff/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SMP_MUX_SELECT_A+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SMP_MUX_SELECT_A+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SMP_MUX_SELECT_B+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SMP_MUX_SELECT_B+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SMP_MUX_SELECT_C+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SMP_MUX_SELECT_C+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SMP_MUX_SELECT_D+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x00) - U200(HFD201[0])/SMP_MUX_SELECT_D+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x34) - U200(HFD201[0])/SPARE_1+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x34) - U200(HFD201[0])/SPARE_1+0x000 exp/act 0xfe/0x0

Wlk1HWMismatch (0x34) - U200(HFD201[0])/SPARE_1+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x34) - U200(HFD201[0])/SPARE_1+0x000 exp/act 0xfd/0x0

Wlk1HWMismatch (0x34) - U200(HFD201[0])/SPARE_1+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x34) - U200(HFD201[0])/SPARE_1+0x000 exp/act 0xfb/0x0

Wlk1HWMismatch (0x34) - U200(HFD201[0])/SPARE_1+0x000 exp/act 0x8/0x0

Wlk1HWMismatch (0x34) - U200(HFD201[0])/SPARE_1+0x000 exp/act 0xf7/0x0

Wlk1HWMismatch (0x34) - U200(HFD201[0])/SPARE_1+0x000 exp/act 0x10/0x0

Wlk1HWMismatch (0x34) - U200(HFD201[0])/SPARE_1+0x000 exp/act 0xef/0x0

Wlk1HWMismatch (0x34) - U200(HFD201[0])/SPARE_1+0x000 exp/act 0x20/0x0

Wlk1HWMismatch (0x34) - U200(HFD201[0])/SPARE_1+0x000 exp/act 0xdf/0x0

Wlk1HWMismatch (0x34) - U200(HFD201[0])/SPARE_1+0x000 exp/act 0x40/0x0

Wlk1HWMismatch (0x34) - U200(HFD201[0])/SPARE_1+0x000 exp/act 0xbf/0x0

Wlk1HWMismatch (0x34) - U200(HFD201[0])/SPARE_1+0x000 exp/act 0x80/0x0

Wlk1HWMismatch (0x34) - U200(HFD201[0])/SPARE_1+0x000 exp/act 0x7f/0x0

Wlk1HWMismatch (0x34) - U200(HFD201[0])/SPARE_1+0x000 exp/act 0xff/0x0

Wlk1HWMismatch (0x35) - U200(HFD201[0])/SPARE_2+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x35) - U200(HFD201[0])/SPARE_2+0x000 exp/act 0xfe/0x0

Wlk1HWMismatch (0x35) - U200(HFD201[0])/SPARE_2+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x35) - U200(HFD201[0])/SPARE_2+0x000 exp/act 0xfd/0x0

Wlk1HWMismatch (0x35) - U200(HFD201[0])/SPARE_2+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x35) - U200(HFD201[0])/SPARE_2+0x000 exp/act 0xfb/0x0

Wlk1HWMismatch (0x35) - U200(HFD201[0])/SPARE_2+0x000 exp/act 0x8/0x0

Wlk1HWMismatch (0x35) - U200(HFD201[0])/SPARE_2+0x000 exp/act 0xf7/0x0

Wlk1HWMismatch (0x35) - U200(HFD201[0])/SPARE_2+0x000 exp/act 0x10/0x0

Wlk1HWMismatch (0x35) - U200(HFD201[0])/SPARE_2+0x000 exp/act 0xef/0x0

Wlk1HWMismatch (0x35) - U200(HFD201[0])/SPARE_2+0x000 exp/act 0x20/0x0

Wlk1HWMismatch (0x35) - U200(HFD201[0])/SPARE_2+0x000 exp/act 0xdf/0x0

Wlk1HWMismatch (0x35) - U200(HFD201[0])/SPARE_2+0x000 exp/act 0x40/0x0

Wlk1HWMismatch (0x35) - U200(HFD201[0])/SPARE_2+0x000 exp/act 0xbf/0x0

Wlk1HWMismatch (0x35) - U200(HFD201[0])/SPARE_2+0x000 exp/act 0x80/0x0

Wlk1HWMismatch (0x35) - U200(HFD201[0])/SPARE_2+0x000 exp/act 0x7f/0x0

Wlk1HWMismatch (0x35) - U200(HFD201[0])/SPARE_2+0x000 exp/act 0xff/0x0

Wlk1HWMismatch (0x36) - U200(HFD201[0])/SPARE_3+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x36) - U200(HFD201[0])/SPARE_3+0x000 exp/act 0xfe/0x0

Wlk1HWMismatch (0x36) - U200(HFD201[0])/SPARE_3+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x36) - U200(HFD201[0])/SPARE_3+0x000 exp/act 0xfd/0x0

Wlk1HWMismatch (0x36) - U200(HFD201[0])/SPARE_3+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x36) - U200(HFD201[0])/SPARE_3+0x000 exp/act 0xfb/0x0

Wlk1HWMismatch (0x36) - U200(HFD201[0])/SPARE_3+0x000 exp/act 0x8/0x0

Wlk1HWMismatch (0x36) - U200(HFD201[0])/SPARE_3+0x000 exp/act 0xf7/0x0

Wlk1HWMismatch (0x36) - U200(HFD201[0])/SPARE_3+0x000 exp/act 0x10/0x0

Wlk1HWMismatch (0x36) - U200(HFD201[0])/SPARE_3+0x000 exp/act 0xef/0x0

Wlk1HWMismatch (0x36) - U200(HFD201[0])/SPARE_3+0x000 exp/act 0x20/0x0

Wlk1HWMismatch (0x36) - U200(HFD201[0])/SPARE_3+0x000 exp/act 0xdf/0x0

Wlk1HWMismatch (0x36) - U200(HFD201[0])/SPARE_3+0x000 exp/act 0x40/0x0

Wlk1HWMismatch (0x36) - U200(HFD201[0])/SPARE_3+0x000 exp/act 0xbf/0x0

Wlk1HWMismatch (0x36) - U200(HFD201[0])/SPARE_3+0x000 exp/act 0x80/0x0

Wlk1HWMismatch (0x36) - U200(HFD201[0])/SPARE_3+0x000 exp/act 0x7f/0x0

Wlk1HWMismatch (0x36) - U200(HFD201[0])/SPARE_3+0x000 exp/act 0xff/0x0

Wlk1HWMismatch (0x37) - U200(HFD201[0])/SPARE_4+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x37) - U200(HFD201[0])/SPARE_4+0x000 exp/act 0xfe/0x0

Wlk1HWMismatch (0x37) - U200(HFD201[0])/SPARE_4+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x37) - U200(HFD201[0])/SPARE_4+0x000 exp/act 0xfd/0x0

Wlk1HWMismatch (0x37) - U200(HFD201[0])/SPARE_4+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x37) - U200(HFD201[0])/SPARE_4+0x000 exp/act 0xfb/0x0

Wlk1HWMismatch (0x37) - U200(HFD201[0])/SPARE_4+0x000 exp/act 0x8/0x0

Wlk1HWMismatch (0x37) - U200(HFD201[0])/SPARE_4+0x000 exp/act 0xf7/0x0

Wlk1HWMismatch (0x37) - U200(HFD201[0])/SPARE_4+0x000 exp/act 0x10/0x0

Wlk1HWMismatch (0x37) - U200(HFD201[0])/SPARE_4+0x000 exp/act 0xef/0x0

Wlk1HWMismatch (0x37) - U200(HFD201[0])/SPARE_4+0x000 exp/act 0x20/0x0

Wlk1HWMismatch (0x37) - U200(HFD201[0])/SPARE_4+0x000 exp/act 0xdf/0x0

Wlk1HWMismatch (0x37) - U200(HFD201[0])/SPARE_4+0x000 exp/act 0x40/0x0

Wlk1HWMismatch (0x37) - U200(HFD201[0])/SPARE_4+0x000 exp/act 0xbf/0x0

Wlk1HWMismatch (0x37) - U200(HFD201[0])/SPARE_4+0x000 exp/act 0x80/0x0

Wlk1HWMismatch (0x37) - U200(HFD201[0])/SPARE_4+0x000 exp/act 0x7f/0x0

Wlk1HWMismatch (0x37) - U200(HFD201[0])/SPARE_4+0x000 exp/act 0xff/0x0

Wlk1HWMismatch (0x38) - U200(HFD201[0])/SPARE_5+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x38) - U200(HFD201[0])/SPARE_5+0x000 exp/act 0xfe/0x0

Wlk1HWMismatch (0x38) - U200(HFD201[0])/SPARE_5+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x38) - U200(HFD201[0])/SPARE_5+0x000 exp/act 0xfd/0x0

Wlk1HWMismatch (0x38) - U200(HFD201[0])/SPARE_5+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x38) - U200(HFD201[0])/SPARE_5+0x000 exp/act 0xfb/0x0

Wlk1HWMismatch (0x38) - U200(HFD201[0])/SPARE_5+0x000 exp/act 0x8/0x0

Wlk1HWMismatch (0x38) - U200(HFD201[0])/SPARE_5+0x000 exp/act 0xf7/0x0

Wlk1HWMismatch (0x38) - U200(HFD201[0])/SPARE_5+0x000 exp/act 0x10/0x0

Wlk1HWMismatch (0x38) - U200(HFD201[0])/SPARE_5+0x000 exp/act 0xef/0x0

Wlk1HWMismatch (0x38) - U200(HFD201[0])/SPARE_5+0x000 exp/act 0x20/0x0

Wlk1HWMismatch (0x38) - U200(HFD201[0])/SPARE_5+0x000 exp/act 0xdf/0x0

Wlk1HWMismatch (0x38) - U200(HFD201[0])/SPARE_5+0x000 exp/act 0x40/0x0

Wlk1HWMismatch (0x38) - U200(HFD201[0])/SPARE_5+0x000 exp/act 0xbf/0x0

Wlk1HWMismatch (0x38) - U200(HFD201[0])/SPARE_5+0x000 exp/act 0x80/0x0

Wlk1HWMismatch (0x38) - U200(HFD201[0])/SPARE_5+0x000 exp/act 0x7f/0x0

Wlk1HWMismatch (0x38) - U200(HFD201[0])/SPARE_5+0x000 exp/act 0xff/0x0

Wlk1HWMismatch (0x32) - U200(HFD201[0])/SYNTH_FILT_DAC+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x32) - U200(HFD201[0])/SYNTH_FILT_DAC+0x000 exp/act 0xfe/0x0

Wlk1HWMismatch (0x32) - U200(HFD201[0])/SYNTH_FILT_DAC+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x32) - U200(HFD201[0])/SYNTH_FILT_DAC+0x000 exp/act 0xfd/0x0

Wlk1HWMismatch (0x32) - U200(HFD201[0])/SYNTH_FILT_DAC+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x32) - U200(HFD201[0])/SYNTH_FILT_DAC+0x000 exp/act 0xfb/0x0

Wlk1HWMismatch (0x32) - U200(HFD201[0])/SYNTH_FILT_DAC+0x000 exp/act 0x8/0x0

Wlk1HWMismatch (0x32) - U200(HFD201[0])/SYNTH_FILT_DAC+0x000 exp/act 0xf7/0x0

Wlk1HWMismatch (0x32) - U200(HFD201[0])/SYNTH_FILT_DAC+0x000 exp/act 0x10/0x0

Wlk1HWMismatch (0x32) - U200(HFD201[0])/SYNTH_FILT_DAC+0x000 exp/act 0xef/0x0

Wlk1HWMismatch (0x32) - U200(HFD201[0])/SYNTH_FILT_DAC+0x000 exp/act 0x20/0x0

Wlk1HWMismatch (0x32) - U200(HFD201[0])/SYNTH_FILT_DAC+0x000 exp/act 0xdf/0x0

Wlk1HWMismatch (0x32) - U200(HFD201[0])/SYNTH_FILT_DAC+0x000 exp/act 0x40/0x0

Wlk1HWMismatch (0x32) - U200(HFD201[0])/SYNTH_FILT_DAC+0x000 exp/act 0xbf/0x0

Wlk1HWMismatch (0x32) - U200(HFD201[0])/SYNTH_FILT_DAC+0x000 exp/act 0x80/0x0

Wlk1HWMismatch (0x32) - U200(HFD201[0])/SYNTH_FILT_DAC+0x000 exp/act 0x7f/0x0

Wlk1HWMismatch (0x32) - U200(HFD201[0])/SYNTH_FILT_DAC+0x000 exp/act 0xff/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0xffe/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0xffd/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0xffb/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0x8/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0xff7/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0x10/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0xfef/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0x20/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0xfdf/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0x40/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0xfbf/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0x80/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0xf7f/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0x100/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0xeff/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0x200/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0xdff/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0x400/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0xbff/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0x800/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0x7ff/0x0

Wlk1HWMismatch (0x31) - U200(HFD201[0])/SYNTH_TUNE_DAC+0x000 exp/act 0xfff/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x7fe/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x7fd/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x7fb/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x8/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x7f7/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x10/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x7ef/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x20/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x7df/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x40/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x7bf/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x80/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x77f/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x100/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x6ff/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x200/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x5ff/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x400/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x3ff/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL+0x000 exp/act 0x7ff/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL_BLOCK+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL_BLOCK+0x000 exp/act 0x6/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL_BLOCK+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL_BLOCK+0x000 exp/act 0x5/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL_BLOCK+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL_BLOCK+0x000 exp/act 0x3/0x0

Wlk1HWMismatch (0x70) - U200(HFD201[0])/TEST_BUS_SEL_BLOCK+0x000 exp/act 0x7/0x0

Wlk1HWMismatch (0x21) - U200(HFD201[0])/TEST_SIG_DAC_A+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x21) - U200(HFD201[0])/TEST_SIG_DAC_A+0x000 exp/act 0xfe/0x0

Wlk1HWMismatch (0x21) - U200(HFD201[0])/TEST_SIG_DAC_A+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x21) - U200(HFD201[0])/TEST_SIG_DAC_A+0x000 exp/act 0xfd/0x0

Wlk1HWMismatch (0x21) - U200(HFD201[0])/TEST_SIG_DAC_A+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x21) - U200(HFD201[0])/TEST_SIG_DAC_A+0x000 exp/act 0xfb/0x0

Wlk1HWMismatch (0x21) - U200(HFD201[0])/TEST_SIG_DAC_A+0x000 exp/act 0x8/0x0

Wlk1HWMismatch (0x21) - U200(HFD201[0])/TEST_SIG_DAC_A+0x000 exp/act 0xf7/0x0

Wlk1HWMismatch (0x21) - U200(HFD201[0])/TEST_SIG_DAC_A+0x000 exp/act 0x10/0x0

Wlk1HWMismatch (0x21) - U200(HFD201[0])/TEST_SIG_DAC_A+0x000 exp/act 0xef/0x0

Wlk1HWMismatch (0x21) - U200(HFD201[0])/TEST_SIG_DAC_A+0x000 exp/act 0x20/0x0

Wlk1HWMismatch (0x21) - U200(HFD201[0])/TEST_SIG_DAC_A+0x000 exp/act 0xdf/0x0

Wlk1HWMismatch (0x21) - U200(HFD201[0])/TEST_SIG_DAC_A+0x000 exp/act 0x40/0x0

Wlk1HWMismatch (0x21) - U200(HFD201[0])/TEST_SIG_DAC_A+0x000 exp/act 0xbf/0x0

Wlk1HWMismatch (0x21) - U200(HFD201[0])/TEST_SIG_DAC_A+0x000 exp/act 0x80/0x0

Wlk1HWMismatch (0x21) - U200(HFD201[0])/TEST_SIG_DAC_A+0x000 exp/act 0x7f/0x0

Wlk1HWMismatch (0x21) - U200(HFD201[0])/TEST_SIG_DAC_A+0x000 exp/act 0xff/0x0

Wlk1HWMismatch (0x22) - U200(HFD201[0])/TEST_SIG_DAC_B+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x22) - U200(HFD201[0])/TEST_SIG_DAC_B+0x000 exp/act 0xfe/0x0

Wlk1HWMismatch (0x22) - U200(HFD201[0])/TEST_SIG_DAC_B+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x22) - U200(HFD201[0])/TEST_SIG_DAC_B+0x000 exp/act 0xfd/0x0

Wlk1HWMismatch (0x22) - U200(HFD201[0])/TEST_SIG_DAC_B+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x22) - U200(HFD201[0])/TEST_SIG_DAC_B+0x000 exp/act 0xfb/0x0

Wlk1HWMismatch (0x22) - U200(HFD201[0])/TEST_SIG_DAC_B+0x000 exp/act 0x8/0x0

Wlk1HWMismatch (0x22) - U200(HFD201[0])/TEST_SIG_DAC_B+0x000 exp/act 0xf7/0x0

Wlk1HWMismatch (0x22) - U200(HFD201[0])/TEST_SIG_DAC_B+0x000 exp/act 0x10/0x0

Wlk1HWMismatch (0x22) - U200(HFD201[0])/TEST_SIG_DAC_B+0x000 exp/act 0xef/0x0

Wlk1HWMismatch (0x22) - U200(HFD201[0])/TEST_SIG_DAC_B+0x000 exp/act 0x20/0x0

Wlk1HWMismatch (0x22) - U200(HFD201[0])/TEST_SIG_DAC_B+0x000 exp/act 0xdf/0x0

Wlk1HWMismatch (0x22) - U200(HFD201[0])/TEST_SIG_DAC_B+0x000 exp/act 0x40/0x0

Wlk1HWMismatch (0x22) - U200(HFD201[0])/TEST_SIG_DAC_B+0x000 exp/act 0xbf/0x0

Wlk1HWMismatch (0x22) - U200(HFD201[0])/TEST_SIG_DAC_B+0x000 exp/act 0x80/0x0

Wlk1HWMismatch (0x22) - U200(HFD201[0])/TEST_SIG_DAC_B+0x000 exp/act 0x7f/0x0

Wlk1HWMismatch (0x22) - U200(HFD201[0])/TEST_SIG_DAC_B+0x000 exp/act 0xff/0x0

Wlk1HWMismatch (0x23) - U200(HFD201[0])/TEST_SIG_DAC_C+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x23) - U200(HFD201[0])/TEST_SIG_DAC_C+0x000 exp/act 0xfe/0x0

Wlk1HWMismatch (0x23) - U200(HFD201[0])/TEST_SIG_DAC_C+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x23) - U200(HFD201[0])/TEST_SIG_DAC_C+0x000 exp/act 0xfd/0x0

Wlk1HWMismatch (0x23) - U200(HFD201[0])/TEST_SIG_DAC_C+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x23) - U200(HFD201[0])/TEST_SIG_DAC_C+0x000 exp/act 0xfb/0x0

Wlk1HWMismatch (0x23) - U200(HFD201[0])/TEST_SIG_DAC_C+0x000 exp/act 0x8/0x0

Wlk1HWMismatch (0x23) - U200(HFD201[0])/TEST_SIG_DAC_C+0x000 exp/act 0xf7/0x0

Wlk1HWMismatch (0x23) - U200(HFD201[0])/TEST_SIG_DAC_C+0x000 exp/act 0x10/0x0

Wlk1HWMismatch (0x23) - U200(HFD201[0])/TEST_SIG_DAC_C+0x000 exp/act 0xef/0x0

Wlk1HWMismatch (0x23) - U200(HFD201[0])/TEST_SIG_DAC_C+0x000 exp/act 0x20/0x0

Wlk1HWMismatch (0x23) - U200(HFD201[0])/TEST_SIG_DAC_C+0x000 exp/act 0xdf/0x0

Wlk1HWMismatch (0x23) - U200(HFD201[0])/TEST_SIG_DAC_C+0x000 exp/act 0x40/0x0

Wlk1HWMismatch (0x23) - U200(HFD201[0])/TEST_SIG_DAC_C+0x000 exp/act 0xbf/0x0

Wlk1HWMismatch (0x23) - U200(HFD201[0])/TEST_SIG_DAC_C+0x000 exp/act 0x80/0x0

Wlk1HWMismatch (0x23) - U200(HFD201[0])/TEST_SIG_DAC_C+0x000 exp/act 0x7f/0x0

Wlk1HWMismatch (0x23) - U200(HFD201[0])/TEST_SIG_DAC_C+0x000 exp/act 0xff/0x0

Wlk1HWMismatch (0x24) - U200(HFD201[0])/TEST_SIG_DAC_D+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x24) - U200(HFD201[0])/TEST_SIG_DAC_D+0x000 exp/act 0xfe/0x0

Wlk1HWMismatch (0x24) - U200(HFD201[0])/TEST_SIG_DAC_D+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x24) - U200(HFD201[0])/TEST_SIG_DAC_D+0x000 exp/act 0xfd/0x0

Wlk1HWMismatch (0x24) - U200(HFD201[0])/TEST_SIG_DAC_D+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x24) - U200(HFD201[0])/TEST_SIG_DAC_D+0x000 exp/act 0xfb/0x0

Wlk1HWMismatch (0x24) - U200(HFD201[0])/TEST_SIG_DAC_D+0x000 exp/act 0x8/0x0

Wlk1HWMismatch (0x24) - U200(HFD201[0])/TEST_SIG_DAC_D+0x000 exp/act 0xf7/0x0

Wlk1HWMismatch (0x24) - U200(HFD201[0])/TEST_SIG_DAC_D+0x000 exp/act 0x10/0x0

Wlk1HWMismatch (0x24) - U200(HFD201[0])/TEST_SIG_DAC_D+0x000 exp/act 0xef/0x0

Wlk1HWMismatch (0x24) - U200(HFD201[0])/TEST_SIG_DAC_D+0x000 exp/act 0x20/0x0

Wlk1HWMismatch (0x24) - U200(HFD201[0])/TEST_SIG_DAC_D+0x000 exp/act 0xdf/0x0

Wlk1HWMismatch (0x24) - U200(HFD201[0])/TEST_SIG_DAC_D+0x000 exp/act 0x40/0x0

Wlk1HWMismatch (0x24) - U200(HFD201[0])/TEST_SIG_DAC_D+0x000 exp/act 0xbf/0x0

Wlk1HWMismatch (0x24) - U200(HFD201[0])/TEST_SIG_DAC_D+0x000 exp/act 0x80/0x0

Wlk1HWMismatch (0x24) - U200(HFD201[0])/TEST_SIG_DAC_D+0x000 exp/act 0x7f/0x0

Wlk1HWMismatch (0x24) - U200(HFD201[0])/TEST_SIG_DAC_D+0x000 exp/act 0xff/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SELECT+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SELECT+0x000 exp/act 0xfe/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SELECT+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SELECT+0x000 exp/act 0xfd/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SELECT+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SELECT+0x000 exp/act 0xfb/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SELECT+0x000 exp/act 0x8/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SELECT+0x000 exp/act 0xf7/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SELECT+0x000 exp/act 0x10/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SELECT+0x000 exp/act 0xef/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SELECT+0x000 exp/act 0x20/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SELECT+0x000 exp/act 0xdf/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SELECT+0x000 exp/act 0x40/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SELECT+0x000 exp/act 0xbf/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SELECT+0x000 exp/act 0x80/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SELECT+0x000 exp/act 0x7f/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SELECT+0x000 exp/act 0xff/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SEL_A+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SEL_A+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SEL_A+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SEL_A+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SEL_A+0x000 exp/act 0x3/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SEL_B+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SEL_B+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SEL_B+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SEL_B+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SEL_B+0x000 exp/act 0x3/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SEL_C+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SEL_C+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SEL_C+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SEL_C+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SEL_C+0x000 exp/act 0x3/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SEL_D+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SEL_D+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SEL_D+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SEL_D+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x20) - U200(HFD201[0])/TEST_SIG_SEL_D+0x000 exp/act 0x3/0x0

Wlk1HWMismatch (0x10) - U200(HFD201[0])/TH_CONTROL+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x10) - U200(HFD201[0])/TH_CONTROL+0x000 exp/act 0x1e/0x0

Wlk1HWMismatch (0x10) - U200(HFD201[0])/TH_CONTROL+0x000 exp/act 0x2/0x0

Wlk1HWMismatch (0x10) - U200(HFD201[0])/TH_CONTROL+0x000 exp/act 0x1d/0x0

Wlk1HWMismatch (0x10) - U200(HFD201[0])/TH_CONTROL+0x000 exp/act 0x4/0x0

Wlk1HWMismatch (0x10) - U200(HFD201[0])/TH_CONTROL+0x000 exp/act 0x1b/0x0

Wlk1HWMismatch (0x10) - U200(HFD201[0])/TH_CONTROL+0x000 exp/act 0x8/0x0

Wlk1HWMismatch (0x10) - U200(HFD201[0])/TH_CONTROL+0x000 exp/act 0x17/0x0

Wlk1HWMismatch (0x10) - U200(HFD201[0])/TH_CONTROL+0x000 exp/act 0x10/0x0

Wlk1HWMismatch (0x10) - U200(HFD201[0])/TH_CONTROL+0x000 exp/act 0xf/0x0

Wlk1HWMismatch (0x10) - U200(HFD201[0])/TH_CONTROL+0x000 exp/act 0x1f/0x0

Wlk1HWMismatch (0x10) - U200(HFD201[0])/ZMUX_DISABLE+0x000 exp/act 0x1/0x0

Wlk1HWMismatch (0x10) - U200(HFD201[0])/ZMUX_DISABLE+0x000 exp/act 0x1/0x0
       *** TEST FAILED ***
     Test execution time 0.21408 sec
diagMgr:diagLogFailure: Fri Dec 20 23:06:08 2024 D Pu=2 T=-127 "DataLineTstStepFail- U200(HFD201[0])/SPARE_0+0x000 exp/act 0x1/0x0"
Test "225" - Registers-->Acquisition-->ADC started
     Test execution time 0.010165 sec
Test "226" - Registers-->Acquisition-->DAC started
     Test execution time 0.42803 sec
Test "227" - Registers-->Acquisition-->Demux started
     Test execution time 0.0046355 sec
Test "231" - Registers-->Trigger-->SBTL started
     Test execution time 8.6603e-005 sec
Test "232" - Registers-->Trigger-->SGTL started
     Test execution time 0.01268 sec
Test "233" - Registers-->Trigger-->TrigComp started
     Test execution time 0.011714 sec
Test "234" - Registers-->Trigger-->CommTrig started
     Test execution time 0.57148 sec
Test "241" - Registers-->Misc-->FanCtrl started
     Test execution time 0.43045 sec
Test "311" - Acquisition-->Demux-->RunAB started
     Test execution time 0.21265 sec
Test "312" - Acquisition-->Demux-->AcqDone started
     Test execution time 0.00092665 sec
Test "313" - Acquisition-->Demux-->SysRdy started
     Test execution time 0.00055677 sec
Test "314" - Acquisition-->Demux-->Interrupt started
     Test execution time 0.0010096 sec
Test "315" - Acquisition-->Demux-->IdcLoSpeed started
     Test execution time 0.0032996 sec
Test "316" - Acquisition-->Demux-->IdcHiSpeed started
     Test execution time 0.11145 sec
Test "317" - Acquisition-->Demux-->IdcAcqDataXfr started
     Test execution time 0.002733 sec
Test "318" - Acquisition-->Demux-->IdcDispDataXfr started
     Test execution time 0.0027344 sec
Test "321" - Acquisition-->Dma-->PaDma started
     Test execution time 0.0024484 sec
Test "322" - Acquisition-->Dma-->IdcAcqDma started
     Test execution time 0.0031037 sec
Test "331" - Acquisition-->Memory-->MemData started
     Test execution time 0.010492 sec
Test "332" - Acquisition-->Memory-->MemAddr started
     Test execution time 0.0019681 sec
Test "333" - Acquisition-->Memory-->MemSpeed started
     Test execution time 11.094 sec
Test "341" - Acquisition-->Vertical-->Preamp Inputs started
       *** TEST N/A FOR THIS HW ***
     Test execution time 1.9556e-006 sec
Test "342" - Acquisition-->Vertical-->TH Inputs started
U200(HFD201[0]) input IN_A failed at high/low input level (ref:0000 hi:0000 lo:0000 mar:10000)
U200(HFD201[0]) input IN_B failed at high/low input level (ref:0000 hi:0000 lo:0000 mar:10000)
U200(HFD201[0]) input IN_C failed at high/low input level (ref:0000 hi:0000 lo:0000 mar:10000)
U200(HFD201[0]) input IN_D failed at high/low input level (ref:0000 hi:0000 lo:0000 mar:10000)
       *** TEST FAILED ***
     Test execution time 0.30627 sec
diagMgr:diagLogFailure: Fri Dec 20 23:06:08 2024 D Pu=2 T=-127 "U200(HFD201[0]) input IN_A failed at high/low input level (ref:0000 hi:0000 lo:0000 mar:10000)"
Test "343" - Acquisition-->Vertical-->ADC Inputs started
U10_A(HFD204[0]) input IN2 failed at low input level (ref:813b18 hi:813c4f lo:813ba4 mar:0100)
       *** TEST FAILED ***
     Test execution time 0.75759 sec
diagMgr:diagLogFailure: Fri Dec 20 23:06:08 2024 D Pu=2 T=-127 "U10_A(HFD204[0]) input IN2 failed at low input level (ref:813b18 hi:813c4f lo:813ba4 mar:0100)"
Test "344" - Acquisition-->Vertical-->ADC Outputs started
     Test execution time 0.23422 sec
Test "345" - Acquisition-->Vertical-->50ohmOvld started
     Test execution time 1.0732 sec
Test "346" - Acquisition-->Vertical-->LFComp started
     Test execution time 0.83658 sec
Test "351" - Acquisition-->PLL-->Clock Freq started
     Test execution time 0.67067 sec
Test "361" - Acquisition-->HFSource-->SINE started
HFSource:SINE:INTLV_CAL_VCO_N CH1 failed, amplitude too low (Act delta:1.386e-001; hi:-1.980e-001 lo:-3.366e-001; Exp Delta min:1.720e-001)
       *** TEST FAILED ***
     Test execution time 0.049042 sec
diagMgr:diagLogFailure: Fri Dec 20 23:06:08 2024 D Pu=2 T=-127 "HFSource:SINE:INTLV_CAL_VCO_N CH1 failed, amplitude too low (Act delta:1.386e-001; hi:-1.980e-001 lo:-3.366e-001; Exp Delta min:1.720e-001)"
Test "362" - Acquisition-->HFSource-->SINE33 started
HFSource:SINE33:ACQ_PHASE_CAL_CLK CH1 failed, amplitude too low (Act delta:1.426e-001; hi:-2.099e-001 lo:-3.524e-001; Exp Delta min:2.680e-001)
       *** TEST FAILED ***
     Test execution time 0.049997 sec
diagMgr:diagLogFailure: Fri Dec 20 23:06:08 2024 D Pu=2 T=-127 "HFSource:SINE33:ACQ_PHASE_CAL_CLK CH1 failed, amplitude too low (Act delta:1.426e-001; hi:-2.099e-001 lo:-3.524e-001; Exp Delta min:2.680e-001)"
Test "363" - Acquisition-->HFSource-->SQUARE started
HFSource:SQUARE:HF_LF_CAL_STEP CH1 failed, amplitude too low (Act delta:3.980e-002; hi:-4.219e-001 lo:-4.617e-001; Exp Delta min:4.340e-001)
       *** TEST FAILED ***
     Test execution time 0.05094 sec
diagMgr:diagLogFailure: Fri Dec 20 23:06:08 2024 D Pu=2 T=-127 "HFSource:SQUARE:HF_LF_CAL_STEP CH1 failed, amplitude too low (Act delta:3.980e-002; hi:-4.219e-001 lo:-4.617e-001; Exp Delta min:4.340e-001)"
Test "371" - Acquisition-->AcqProcessor-->SPI started
     Test execution time 0.0001651 sec
Test "372" - Acquisition-->AcqProcessor-->INT Line started
     Test execution time 0.00062606 sec
Test "373" - Acquisition-->AcqProcessor-->Interrupt started
     Test execution time 0.00048917 sec
Test "374" - Acquisition-->AcqProcessor-->RelayDrive started
       *** TEST N/A FOR THIS HW ***
     Test execution time 1.9556e-006 sec
Test "375" - Acquisition-->AcqProcessor-->TWI started
     Test execution time 0.00014248 sec
Test "376" - Acquisition-->AcqProcessor-->PrbInterrupts started
     Test execution time 0.00036709 sec
Test "377" - Acquisition-->AcqProcessor-->TCpowerCtrl started
       *** TEST N/A FOR THIS HW ***
     Test execution time 1.6762e-006 sec
Test "378" - Acquisition-->AcqProcessor-->MAX517 started
     Test execution time 0.00096716 sec
Test "411" - Trigger-->Inputs-->Ch1 started
     Test execution time 0.10322 sec
Test "412" - Trigger-->Inputs-->Ch2 started
     Test execution time 0.11976 sec
Test "413" - Trigger-->Inputs-->Ch3 started
     Test execution time 0.11968 sec
Test "414" - Trigger-->Inputs-->Ch4 started
     Test execution time 0.11995 sec
Test "415" - Trigger-->Inputs-->Line started
     Test execution time 0.016928 sec
Test "416" - Trigger-->Inputs-->Video started
     Test execution time 0.18757 sec
Test "417" - Trigger-->Inputs-->Events started
     Test execution time 0.20396 sec
Test "418" - Trigger-->Inputs-->Serial started
     Test execution time 0.30997 sec
Test "421" - Trigger-->Outputs-->523TrgOut started
     Test execution time 0.00072942 sec
Test "422" - Trigger-->Outputs-->523CpuInt started
     Test execution time 0.00052046 sec
Test "423" - Trigger-->Outputs-->Fedge started
     Test execution time 0.040204 sec
Test "424" - Trigger-->Outputs-->Ftrig started
     Test execution time 0.03961 sec
Test "425" - Trigger-->Outputs-->TrigInfo started
     Test execution time 0.47688 sec
Test "431" - Trigger-->Timers-->Delay started
     Test execution time 0.096932 sec
Test "432" - Trigger-->Timers-->Delta started
     Test execution time 0.047023 sec
Test "433" - Trigger-->Timers-->Holdoff started
     Test execution time 0.10354 sec
Test "434" - Trigger-->Timers-->PostTrig started
     Test execution time 0.15703 sec
Test "435" - Trigger-->Timers-->PreTrig started
     Test execution time 0.057601 sec
Test "436" - Trigger-->Timers-->Timeout started
     Test execution time 0.04074 sec
Test "511" - TekLink-->Topology -->Signals started
 -- The instrument does not have a physical connection to teklink network.
       *** TEST N/A FOR THIS HW ***
     Test execution time 0.00010169 sec
Test "521" - TekLink-->Trigger -->Path started
 -- The instrument does not have a physical connection to teklink network.
       *** TEST N/A FOR THIS HW ***
     Test execution time 0.00010029 sec
Test "531" - TekLink-->Reference -->Path started
 -- The instrument does not have a physical connection to teklink network.
       *** TEST N/A FOR THIS HW ***
     Test execution time 9.9733e-005 sec
Fri Dec 20 23:06:28 2024: DIAG MODE DIAGNOSTICS RESULTS: 6 (of 70) tests SKIPPED
Fri Dec 20 23:06:28 2024: DIAG MODE DIAGNOSTICS RESULTS: 6 (of 64) EXECUTED tests FAILED
Test 224 - F ==> Registers->Acquisition->TrkHld, 0.21408 sec
DataLineTstStepFail- U200(HFD201[0])/SPARE_0+0x000 exp/act 0x1/0x0
Test 342 - F ==> Acquisition->Vertical->TH Inputs, 0.30627 sec
U200(HFD201[0]) input IN_A failed at high/low input level (ref:0000 hi:0000 lo:0000 mar:10000)
Test 343 - F ==> Acquisition->Vertical->ADC Inputs, 0.75759 sec
U10_A(HFD204[0]) input IN2 failed at low input level (ref:813b18 hi:813c4f lo:813ba4 mar:0100)
Test 361 - F ==> Acquisition->HFSource->SINE, 0.049042 sec
HFSource:SINE:INTLV_CAL_VCO_N CH1 failed, amplitude too low (Act delta:1.386e-001; hi:-1.980e-001 lo:-3.366e-001; Exp Delta min:1.720e-001)
Test 362 - F ==> Acquisition->HFSource->SINE33, 0.049997 sec
HFSource:SINE33:ACQ_PHASE_CAL_CLK CH1 failed, amplitude too low (Act delta:1.426e-001; hi:-2.099e-001 lo:-3.524e-001; Exp Delta min:2.680e-001)
Test 363 - F ==> Acquisition->HFSource->SQUARE, 0.05094 sec
HFSource:SQUARE:HF_LF_CAL_STEP CH1 failed, amplitude too low (Act delta:3.980e-002; hi:-4.219e-001 lo:-4.617e-001; Exp Delta min:4.340e-001)
DIAGNOSTIC EXECUTION finished in 19.985 sec
DRAM is Mt_ddr2_512M_667

Dram Calibration results:
-------------------------
DramCal has PASSED on all Demuxs

 -- The instrument does not have a physical connection to teklink network.
pipe 0:4 buf[0]:-128, buf[end]:-1, cross 17983
pipe 0:5 buf[0]:-128, buf[end]:-5, cross 25000
pipe 0:6 buf[0]:-128, buf[end]:-11, cross 25000
pipe 0:7 buf[0]:-128, buf[end]:-11, cross 25000
pipe 0:4 buf[0]:-128, buf[end]:-1, cross 19840
pipe 0:5 buf[0]:-128, buf[end]:-6, cross 25000
pipe 0:6 buf[0]:-128, buf[end]:-11, cross 25000
pipe 0:7 buf[0]:-128, buf[end]:-13, cross 25000
pipe 0:5 buf[0]:-128, buf[end]:-5, cross 25000
pipe 0:6 buf[0]:-128, buf[end]:-11, cross 25000
pipe 0:7 buf[0]:-128, buf[end]:-14, cross 25000
pipe 0:4 buf[0]:-128, buf[end]:-1, cross 14286
pipe 0:5 buf[0]:-128, buf[end]:-6, cross 25000
pipe 0:6 buf[0]:-128, buf[end]:-11, cross 25000
pipe 0:7 buf[0]:-128, buf[end]:-14, cross 25000
can't get a good crossing
Bad cross measurement
Phase cal pass 2
dmx 0 took 32 iterations
dmx 1 took 32 iterations
dmx 2 took 32 iterations
dmx 3 took 32 iterations
pipe 0:4 buf[0]:-128, buf[end]:-2, cross 7413
pipe 0:5 buf[0]:-128, buf[end]:-7, cross 25000
pipe 0:6 buf[0]:-128, buf[end]:-12, cross 25000
pipe 0:7 buf[0]:-128, buf[end]:-13, cross 25000
pipe 0:5 buf[0]:-128, buf[end]:-6, cross 25000
pipe 0:6 buf[0]:-128, buf[end]:-12, cross 25000
pipe 0:7 buf[0]:-128, buf[end]:-12, cross 25000
pipe 0:5 buf[0]:-128, buf[end]:-5, cross 25000
pipe 0:6 buf[0]:-128, buf[end]:-11, cross 25000
pipe 0:7 buf[0]:-128, buf[end]:-13, cross 25000
can't get a good crossing
initial cross   111 chip:quad 0:0
initial cross   107 chip:quad 0:1
initial cross   113 chip:quad 0:2
initial cross   108 chip:quad 0:3
initial cross   118 chip:quad 1:0
initial cross 23873 chip:quad 1:1
Bad cross measurement
Phase cal pass 3
dmx 0 took 32 iterations
dmx 1 took 32 iterations
dmx 2 took 32 iterations
dmx 3 took 32 iterations
can't get a good crossing
initial cross   111 chip:quad 0:0
initial cross   107 chip:quad 0:1
initial cross   114 chip:quad 0:2
initial cross   108 chip:quad 0:3
initial cross   142 chip:quad 1:0
initial cross 23873 chip:quad 1:1
Bad cross measurement
Phase cal pass 4
dmx 0 took 32 iterations
dmx 1 took 32 iterations
dmx 2 took 32 iterations
dmx 3 took 32 iterations
can't get a good crossing
initial cross   111 chip:quad 0:0
initial cross   107 chip:quad 0:1
initial cross   113 chip:quad 0:2
initial cross   108 chip:quad 0:3
initial cross   118 chip:quad 1:0
initial cross 23873 chip:quad 1:1
Bad cross measurement

ERROR (0xffffffff): digPhaseCal failed

--- End code ---
iAleks:
Downlod here console.txt file.
On previous photo i see your acqusition board without track and hold ic (its U200), look like tekscope program trying get access to u200.
Try delete callibration file C:\TekScope\calibration   >calSPCConst.dat< then restart scope
pasta2018:
Hi iAleks,thanks for your advise.I delete calibration file and restart,the errors didn's change.
I upload the console.txt file here.
Navigation
Message Index
Next page
Previous page
There was an error while thanking
Thanking...

Go to full version
Powered by SMFPacks Advanced Attachments Uploader Mod