Understanding and Repairing Clock Generator on Adret 742A UHF Generator

[PerArdua]

Hi,

I'm currently attempting a repair of an Adret 742A UHF Generator. I've identified a number of issues, not limited to numerous blown capacitors, broken ICs, significant damage from a leaked NiMh battery pack, etc. At this stage I have repaired the damage to the CPU PCB caused by the battery leak, and verified correct connections etc. As part of testing, I am trying to create a sensible looking CPU EXTAL signal by powering just the system OCXO and CPU clock generator portion of the CPU PCB external from the instrument.

The schematic for the CPU PCB can be found on pages 17 and 18 here: http://ftb.ko4bb.com/manuals/188.222.43.3/ADRET_742M1_RF_Generator_Service_Manual.pdf with PCB layout and component list on the following pages.

The clock circuit unfortunately lies over two separate pages, for convenience I have attached a joined up and streamlined version of the clock circuit below.

I have ascertained that a 10 MHz signal from the OCXO enters the CPU bord through pins 15 and 17 of the CPU board's main connector (bottom of page 18). It is then converted into a single-ended signal before being buffered/inverted by a 74LS04N before clocking a 74LS196N ripple counter. This counter effectively performs a division by 2.5 on the 10 MHz signal, producing asignal that is periodic over three non periodic pulses. This signal is the filtered by an LC bandpass filter with a centre tapped transformer (T3). This filter is somewhat tunable as T3 is inside a metal can with a tuneable ferrite cap. The output signal is buffered again by Q3 and inverted by the 74LS04. This should produce a 4 MHz EXTAL signal for the 6802 CPU.

Unfortunately, the battery leak had completely destroyed the windings of T3. The components list simply lists T3 as a 15+2x7 turns F10B transformer. I have assumed this means 7 turns either side of the centre tap, and 15 turns on the single side. I rewound the transformer in a relatively neat job and managed to assemble it into the can without too much issue.

During my initial tests, I found both the 74LS04N and 74LS196N ICs were faulty. Replacing them with new parts (I have replaced all components with new versions, excluding T2 which survived unscathed) sourced from a reputable dealer (though I could only find a 74LS196CP) seems to have restored proper functionality of those portions of the circuit. However, the EXTAL signal appeared to be of dismal quality - see image below, obtained whilst measuring the EXTAL net of the 6802, with 6802 removed from the PCB. The 6802 datasheet (https://www.jameco.com/Jameco/Products/ProdDS/43502.pdf page 3) suggests that Vhigh-min would be 2V - clearly this runs the risk of incorrectly clocking the 6802.

I removed T3 from the circuit and measured the inductance of each winding. both of the tapped windings were identical, between 1.0uH to 1.5uH with the ferrite cap fully screwed in. The single side winding measured between 3.4uH to 5.3uH. I used these values in a SPICE simulation (attached, along with a CSV file and plot of a measurement from the output of the 74LS196 being used as the PWL for the voltage source), and found that ideally (assuming 1:2 turns ratio) these values should be around 2.4uH and 4.8uH. I could try rewinding these, but I'm conscious of damaging the old plastic winding loom, and also of not being able to do much better than my first attempt (which was, as far as I'm concerned, pretty neat). As such, I elected to add more capacitance to C5 and C6, effectively lower the centre frequency and narrowing the pass band of the filter. However, the effect on the output was negligible.

I am at a stage where I feel that whilst I understand what the circuit is trying to achieve, I'm not sure I get the 'why' or 'how'. I am thinking there might be some system synchronisation that requires the derivation of the CPU clock from the main system OCXO, rather than using a standalone XTAL - what that is though, I have no idea. unfortunately all documentation is in French and extremely hard to come by. I have only found a small handful of mentions of this instrument on the internet. Secondly, I am not sure as to what signal is 'sufficient' - I cannot see it producing a periodic 4 MHz signal (rather a 4Mhz signal averaged over some time period), but in that case - why filter the output from the 196? Why not feed directly the 6802 from the 196? At this stage, I am considering using the output from T3 (Q3 base - below) to drive a high speed comparator with hysteresis to produce a clean EXTAL signal, but then this wouldn't be much different from using the 196 output directly.

I'm a bit confused as to what next step I should take, and open the floor to suggestions and interpretations of the circuit. I do not want to give up on this instrument, and happy to try some alterations (adding a 4 Mhz XTAL, or comparator or whatever), but would like to seek some guidance before I chase too many rabbit holes.

[timeandfrequency]

Hi PerArdua,

[...]I am at a stage where I feel that whilst I understand what the circuit is trying to achieve, I'm not sure I get the 'why' or 'how'. I am thinking there might be some system synchronisation that requires the derivation of the CPU clock from the main system OCXO, rather than using a standalone XTAL - what that is though, I have no idea.[...]

The ADRET 74X Series of RF Generators are build around multiple 'interwinded' PLL loops and the constrain of synchronysing EXTAL with the 10MHz reference clock is a legitimate question.
By the way, fully understanding all of the tricks packed inside ADRET T&M stuff instantaneousy pushes you to the 'electronic guru' level. Every second ADRET equipement was a masterpiece and providing explanations and details on how or why is was done that way was not among their mindset. All of the bloc diagrams and schematics are provided, but explanations are sparse. Reparing such a stuff can be a long way to go.

I had a quick look to the CPU board to get a ballpark of its block diagram and also to some other boards where the CPU has to poke in, like the 'Analog board' #0277490000 and the 'Eighty steps board' #0277500000.

One can see that the CPU sets values for CNAs, loop dividers and signal flow registers, but I could not spontaneously identify a synchronization constrain. The CPU updates the registers inside the IC's, writes digital values inside the CNAs, but it seems that this can be done at any time. Once update is done, the numerous PLL loops just lock in using the new divider values, signal path is routed according to the relevant frequency band and mixing scheme and finally the output signal just shows up with correct frequency, level, modulation mode, modulation frequency and modulation depth.
-> So I would definitely give it a try with a vanilla 4 MHz TTL oscillator or even a 4 MHz crystal plus two 18pF caps (and also using the XTAL pin).

Why did the ADRET engineers extract the EXTAL signal from the OCXO signal ?
Well, it's a demanding question and the documentation is silent on such matters, so I only have some clues :
- These boat anchors were forged with utmost attention in limiting non-hamonics, sub-harmonics, phase noise and other spurious signals. Synchronysing every internal clock to a master clock probably contributes to maintain those specs at the highest possible level.
- If there's no master clock (internal or external 10MHz), the µC is halted or at least stuck : this also means that any GPIB communication is denied. If this gear is used in an automated test bench, hindering the GPIB data exchange is a strong manner to tell the GPIB Master that something's going wrong with the RF Generator... 


Now, if you prefer not alter the existing circuit and try to make it work as is, here are some hints :

- The hex inverter plus Q3 is more or less used as an analog amplifier pushed into saturation, perhaps with some hysteresis (positive feedback via R11). It's always a bit tedious to adjust the polarization when using logic gates this way. Furthermore, you said you replaced the hex inverter with a new one, which might be internally slighty different to the legacy one.
On your *.asc simulation schematic (nice work !), you put the labels at the correct location where to set the scope probes into the real circuit : at first you might need to maximise the filter output's level (to center it on the 4MHz frequency) and then check at the input of the logic inverter for acceptable signal levels. It's important to avoid as far as possible to have the high and low peak values of the sine signal inside the 'undefined region'  : TTL has the input high level above 2.0 V and the input low level below 0.8 V. So try to fiddle R9, R10 and R11 (± 2 steps of E12 resistor series values) to get the best possible signal at the logic gate input (= well below 0.8V and well above 2V). Use your simulation tool to find which way to act (increase or decrease the resistance values).  I also noticed in your simulation file that the modeling of the inverter's behaviour might not be very faithful : the output signal state change at very high input voltage levels. Fortunately, that's not that important for the circuit health : focus your attention onto the input signal of the logic inverter. Once you have at the input at least a nice sinewave with adequate levels (or even a quite rectangular signal), the ouput shall be fine.

- If the input signal at the logic gate is too weak, maybe that Q3 lacks of gain and needs to be replaced. Prefer using a BC560C ('C' = highest values of hfe, typically 500 @ Ic=2mA)

- Another drawback of feeding a TTL logic input with a 'not square' wave (e.g. sinewave) is its low voltage rate of change which tents to push the gate into a metatstable state. Try to replace your 74LS04N with a 74LS14 which provides the same logic function, same pinout, but with Schmitt-trigger inputs that much better cope with 'slow' changing signals.

[update 1] : corrected the URLs towards the 742 SM pages

[PerArdua]

Hi timeandfrequency,

Thank you so much for you in depth reply - I really appreciate it. In all honesty, i am not sure if this machine is the product of beauty or madness, but that is perhaps more a result of my not being a grey-beard!

I will try with a crystal and two caps, and will see about trying to get the instrument to boot. There are plenty of blown tantalum capacitors on the +15V rail of this instrument - it has had a hard life for sure, but I hope it can return to operation. At that point I may try to get it working with the original circuit, and will try to produce a card extender to allow me to measure and adjust during operation as a system. I will offer a free card extender (I might even offer to pay postage) to someone willing to make some measurements on a good 74X CPU board.

I also intend to purchase a EPROM reader/programmer for the 3 EPROMS (2x CPU Board, 1x in for the attenuator and UHF board) - hopefully they have not degraded, and their contents can be accessible to those attempting future repairs/investigations into these instruments. Do you (or anyone else) have any recommendations for a suitable reader/programmer for the D2764 EPROMs?

I suppose the designers of these instruments are no longer with us? It is a shame that so little documentation exists - at least which I have found from my searches - but maybe more exists on the French side of the internet (my ignorance, sorry).

Thanks again for your time and sharing your knowledge, I will look to attempt the crystal implementation next week and will report back.

[timeandfrequency]

Hi PerArdua,
Thanks for your kind reply.

The guys at ADRET were truly top notch and could easily compare to their peers at HP, TEKTRONIX, GEC-MARCONI and FLUKE. Even if I have limited knowledge on that topic, I would say that the manufacturing quality was better at HP than at ADRET.

Maybe these links can help you to get more information about ADRET :

The Adret story (english translation)

Adret legacy/revival Internet pages (english translation)

About 15 years ago, I remember having setup with another guy a small test by using an ADRET 74X.
Step 1 : By using a really quiet 10MHz reference crystal (sine output), plot its spectrum around the carrier using a high end spectrum analyser (RBW was set to the narrowest available value that was 3 Hz). Even with a tiny frequency span, it takes long minutes to plot the spectrum.
Step 2 : Use this reference crystal as external clock for the 74X, set any frequency value (let's say 500 000 000 Hz), plug the output of the generator into the SA and draw the same spectrum around the 500 MHz carrier.
-> There was no difference between both traces : same shape ! No additional phase noise at the bottom of the carrier. Even with an 10 Hz output frequency resolution, which leads to very high division factors inside a PLL loop (that creates huge amount of jitter), the uncanny frequency addind and mixing scheme inside the 74X actually adds no phase noise. At the end of the seventies, this was a huge achievement. The 1976 ADRET catalog gives some clues about iterative frequency synthesis (see Fig 3). Similar behaviour/specs are now available when carefully using DDS ICs because they do not make use of dividers the same way than those required in PLL loops.

It is a really nice idea to save the EPROMs contents. I would suggest you to get in touch with KO4BB that would for sure appreciate to host the binary files on his Internet site. Please include also in your data package the model and serial number of your equipment.
Also be very careful with these old parts which - due to aging - become very sensitive to electrostatic discharges. So when reading the EPROMs, ground all equipment and wear at least an anti-static wrist strap.

Unfortunately, I have little knowledge about EPROM readers/programmers, but I'm pretty sure that other members on the forum are gurus in that realm and can provide you some clever advice.

For the CPU card revival, once the µC clock is neat, try to power it up (via a lab PS with current limitation), and perhaps also connected to the front panel. Then, by probing both adress an data buses, check for lines that never toggle, which could be a clue for a dead part or a short to GND/VCC.

If you have the required gear, you may also try to communicate with the CPU via its GPIB interface. The message structure and commands are not that complicated (have a look at the bottom of the page).

I will also try to follow your next posts on this adventure.

[DLJ]

Hi PerArdua.
You are correct with the details of the LS196. It divides the 10MHz clock down to 4MHz for the CPU, though it is slightly asymetric, as you noticed.
One little detail that you might have missed is the "rouge - NO clock" led D1, if this is off then you have a running clock. If it is lit then you have problems
There is also an orange "error" led which should stay off, mine flashes occasionally, but that is becasue my Adret is currently faulty

If your EPROMS are 2764 then you will have difficulty finding a programmer that can supply the 21V needed for programming, although reading the data should be fine with alsmost any programmer. However 2764As seem to be supported by the cheap programmers.

I have attached some fresh clk waveforms, look the same as yours.

Hope that helps.
Dave

[PerArdua]

Thanks for the interesting replies both.

timeandfrequency - thank you. I will certainly offer any ROM dumps to K4OBB, as well to a Marconi group on groups.io - hopefully spreading the resources about in a few locations will minimise the risk of them disappearing should a single place go down. Noted your points regards ESD safety, I used a wristband and removed the ICs from the board prior to cleaning. I have placed them all into ESD safe foam to store them safely whilst I have been 'playing' with the board. My only concern is thusfar, both the inverter and counter ICs have been broken - 100% failure rate so far is not too encouraging haha. I have also added IC sockets for all ICs, about a dozen had no socket, and a few sockets were damaged from corrosion.

DLJ - Many thanks for your measurements - it is reassuring to know the output of my 196 now looks reasonable. May I ask if these measurements are from a 196 you have in another circuit/breadboard, or if they are from a 74X CPU board?

The crystal has been ordered and I have figured out where I will place it, minimising damage to the PCB too. Unfortunately I think I will need to vut the EXTAL trace, as I cant remove the buffer IC, and I am not sure about leaving floating circuitry on the clock line. A small cut should allow me to repair it easily in the future.

[DLJ]

The waveforms are from the dark depths of my Adret 740a. Which has an old version CPU, 2114 RAMs and 2732 EPROMs.
Cheers DLJ

[PerArdua]

Wow - a fantastic photo, thank you!

Interestingly that is completely different from the CPU board I have in my 742A - I was under the impression the 740, 742 (maybe even the 730?) shared the same CPU board. My NiMh (where your 2114s are) destroyed much of my PCB. I will post a picture of my repaired board when I install the crystal.

Would you be able to probe the EXTAL pin of the 6802P please? I believe it is pin 39. It would be interesting to know by how much it differs compared to the output from the 196 in your previous scope captures.

[timeandfrequency]

Hi PerArdua,

Socketing your logic ICs is always a good practice (for analog stuff and prescalers it depends). It eases replacement and allows to unplug some of the parts during failure analysis.

Once your CPU clock is clean, you might have a look at Adrian's skills on how to mend faulty CPU boards (in that case a Commodore 64). The interesting part starts at 21:20.






Another Internet site with some ADRET documents.

And also an unique TV report broadcasted in 1987, when Adret joint Schlumberger (download size : 30MB).

One important thing to keep in mind for the 74X Series is that the analog and RF boards are floating against the CPU board ground. A bunch of optocouplers isolate the 'instrument bus' from the native CPU data + adress bus. To avoid any mess, making use of a scope having isolated inputs is of great help when probing simultaneously into the analog/RF sections and the CPU board.

[DLJ]

Hi PerArdua, timeandfrequency.

1) Thanks for the link to the Adret docs - it prompted me to actually do some reading, and I learned something new. The led on the cpu board that I thought was an "error" led is in fact a "occupe" or "busy" led, which explains the flashing that I am seeing. 

2) I have attached a waveform from pin 39 of the CPU, the clock input. A pretty nice 4MHz clock.

Maybe it is time I fixed the RF issues on my 740. 

[PerArdua]

Interesting posts, thanks both.

A clear indication that the filter is supposed to be quite selective of the 4MHz component, thanks for that DLJ. Interestingly I spotted your board's Q3 is the opposite way to mine, using another MPS3640 according to the schematics from t&f's website here https://archives.doctsf.com/documents/feuilleter_document.php?num_doc=52087&ref=39759.

Not to put you on the spot DLJ, but would you feel up to measuring the inductances of T3? As this would involve removing it from the board I'd totally understand if you'd prefer not - no pressure meant at all. I'll be trying the separate 4 MHz crystal next week in any circumstance, though I am suspecting the route of my results is an incorrectly rewound T3. A slight niggle in my mind is that the schematics show an offset centre tap on T3, but the parts list suggests it is even (15+2x7 turns). Maybe artistic licence, but maybe not.

Flashing red = bad, flashing orange = good? That's a nice choice of colour haha.

Timeandfrequency, a fascinating video - I think that is our CPU board going through the wave soldering process as 0:23!

[timeandfrequency]

Hi PerArdua,

I think that is our CPU board going through the wave soldering process as 0:23!

Wow ! You are probably right.

The SM tells that the yellow LED 'occupé' (no mention of orange colour, but for sure it's the right LED) flashes when the µP is busy. So DLJs CPU board is probably in perfect working condition. The 'busy' LED is driven by the 'BUS AVAILABLE (BA)' signal which is at pin 7 of the MC6802.

It might also be interesting to mention that the MPS3640 (Q3) has a much lower current gain than the BC560C (Min value is 30 @ Ic =10mA  vs 380 @ Ic = 2mA). fT is twice as high for the MPS3640. Those parts cannot be considered as equivalent but, nevertheless, the B560C seems to be a better choice.

Indeed, having a deeper look into that section of the schematics shows that Q3 is actually set as an emitter-follower (also named 'common-collector') : this stage provides no voltage gain but only current gain and therefore its function is to decouple T3 from the logic gate input. The less current is drawn from T3, the better it is possible to keep its Q value at a high level, that speaks for better selectivity. So even if T3 is in good health, drawing too much current (and that's also true for the primary windings) creates a burden that hampers its ability to extract the 4 MHz frequency from the broad spectrum signal that comes out of the LS196.

To summmize : T3 might be faulty, but if it's not the case, that means that the surrounduing parts are involved in creating the mess.


And if the failure persists after changing those surrounding parts, the mess might be located below the parts, that is inside the PCB.

You explained that the Ni-Cd battery on your CPU board leaked and that the electrolyte spilled in the area where T3 & Q3 are located. Unfortunately, it might happen that the electrolyte also soaks into the PCB, which ruins its insulation resistance. The electrolyte is now trapped inside the lamination layers and it has to be removed from there.
Maybe other forum members have significant experience about PCB restoration after electrolyte spillage and could provide useful hints. If you want to head towards that direction, maybe that creating a dedicated thread on that topic would help to gather the largest possible audience.

If I had to perform such a restoration, I would proceed as follows. Soak for at least one hour the PCB into an ultrasonic cleaner filled with isopropyl alcohol. This has to be done outdoors  (caution : flammable vapor). Replace the alcohol at least twice and when done, bake the PCB in the kitchen oven for 4 to 6 hours @ 50°C, with (forced) convection turned on.

A bit of SPICE
Applying an FFT to the signal you recorded, which is coming from the LS196 output, confirms that T3 has to act as a rather selective bandpass filter to catch out the wanted 4 MHz carrier. The second strongest signal in the (actually infinite) spectrum is the 6 MHz peak @ -3 dBC and then the 2 MHz peak @ -6.5 dBC.

[DLJ]

Hi PerArdua,

I have tried to measure the impedances of the transformer windings.

I am not super confident of these measurments, but I have repeated the measurments and observed the same results.
Measurments taken using a Marconi TF 2700 (out of calibration by several decades  ).
One winding of 4.5uH
second winding of 7.5uH and 13uH, giving a total of 20uH

I wonder if the Adret description "2x7+15" does not refer to turns, but instead indicate uH, as in one winding of 2uh, and a second consisting of 7uH and 15uH.

Good luck
DLJ

[George Edmonds]

Hi Per Ardua

I really did not want to be involved with this conversation, but as there appears to be a total lack of understanding as to the role of T3 I am reluctantly doing do.

T3 is a simple L/C tuned tank circuit with a resonant frequency of about 4mHz, it forms the band pass filter shown on the block diagram, now given that the parallel capacitance is 164pf the main tuned winding must be in the region of say 11uH, Spice not needed, just a bit of basic tuned circuit theory.

The use of a tapped primary and a small secondary is done to maintain as high a Q (narrow bandwith) of T3 as is possible.

I have tried to make some measurements of T3 from a 742A that I own, these are out of circuit measurements on T3 alone, although repeatable they do not make complete sense.  They were made at a frequency of 100kHz using a Peak LCR45, possibly at still too low a frequency to be accurate, measurements made using the 1khz of a Marconi 2700 were complete nonsense, especially for the secondary.

I found entire primary was 14.97uH
Primary tap to one end was 3.97uH
Primary tap to other end was 8.85uH
Secondary was 3.2uH

Yes I know that these do not add up correctly, but that is what they measure on a virtually new Peak LCR45 and on a number of other LCR meters that I have that operate at 10kHz and above.

If T3 is operating correctly you should be able to adjust it for maximum smoke on the secondary at 4mHz.

With Adret you need to decide if you want to use a signal generator or to spend your time repairing one.  I have repaired a number in the past, but now the two that I own sit in my store unloved and unused.  I use Marconi Instruments kit only for a signal generator as these just simply work.

The best thing that Marconi Instruments ever did was to put Adret of its misery.

G Edmonds G6HIG

[George Edmonds]

Hi Per Ardua

Further to my last I have now had time to look at my printed Adret manuals.

T3 consists of an input winding of 7 Coils with an over wind of 15 Coils, the entire winding is in parallel with 164pf to form a resonant tank circuit at 4mHz.

The output winding is of 7 Coils.

Adret use the term “Spires”, which translates from technical French as Coils.

My measurements also confirm the above.

G Edmonds G6HIG

[PerArdua]

Thank you George for the pointers and measurements, especially of T3.

Apologies for my delay in replying, I have been away at a funeral, and not been well this week.  A short update follows to show I am still (slowly) working on this.

I have powered up the PCB (external of the instrument, not connected to anything other than a bench power supply) and observe a good 4MHz clock on the 6802, however the amber "busy" light does not illuminate. This is tied to the bus available pin of the 6802, such that it is not illuminated when either the !HALT input is in the low state, or the 6802 is a WAIT state as a result of executing a WAIT instruction. On the 742A CPU PCB, the !HALT input is tied to 5V through a 4.7k pull up resistor - I will measure this pin in the next day or two when I feel well. The rest of the CPU pins are in a steady state, so I am reasonably sure that nothing is happening.

I am currently working my way through testing each (logic) IC on the PCB, as best as I can (testing the memory is impossible without a known good dump to compare it with). In either case, I will hopefully have a reader/programmer at the end of the month and will upload what I find.

Thanks again to everyone who has helped. 

[PerArdua]

An update on my progress:

I've tested every IC out of circuit (at least, those that can easily be tested such as buffers, flip flops, gates, etc), and have had some mixed results. The image below shows the results - red X indicates damaged IC, green O indicates a functioning IC, orange ? indicates an IC I am unable to easily test, blue / indicates ICs for GPIB connectivity (not worried about that yet).

Clearly, the ICs around and below the battery are most likely to be damaged - this leaves me feeling a bit 50/50 on the state of the 6800 CPU, ROM, and the 6821 PIA.

The damaged ICs are:

SN05 - 74LS156N - Dual 2 line to 4 line decoder (in the 742A, configured as a 1 to 8 demux)
SN06 - 74LS20N   - Dual 4 input NAND gates
SN07 - 74LS00N   - Quad 2 input NAND gates
SN29 - 74LS374N - Octal D type flip flops

Plus SN01 and SN02 from the clock circuit, but those were identified as damaged earlier.

My plan is to have a look over the rest of the instrument for any obviously damaged components, ensure the power supply outputs the correct voltages etc, and then make a digikey/mouser order to gain new parts. I know for certain the ribbon cables used to jumper the power supply output to the motherboard have been severed (a poor design choice imo), so I will attempt a fix on those after proving the power supply works safely. At that point I will try testing the CPU card again with the new ICs and hopefully see some life. At the end of the month I will also look to purchase a TL866ii plus EPROM reader/programmer - at that point I will be able to at least read the two EPROMs and the EEPROM. Any idea why they might have used the two types of memory?

All the best.

[timeandfrequency]

Hi PerArdua,

Sorry to hear about your predicament, and I wish you to recover soon.

CPU board repair
Electrolyte leaking seems to have been significant and killed many IC's. Before inserting new ICs, I suggest to clean the board thoroughly by applying the process already explained above.


CPU behaviour
I've no knowlege on how the 6802 behaves in a 742A, but, as this gear was designed in the early 80', it shoudn't be deadly complicated. And we don't know either if the CPU board is able to run outside of the unit. Yet, it's better to make some probing while the CPU board is standalone.
After initialization, maybe the whole programming scheme is event driven, just wating for an interrupt to occur on the /IRQ pin, which is tied to the GPIB controller (68448) and the 6821 PIA. The latter communicates with the front panel.


A few hints to check the 6802 (after replacing all of the dead glue logic parts)

- Check if the power supply rail is a clean 5VDC ±5 % (this should be OK thanks to the lab PS, but a nasty high frequency toggling burden can hinder the whole board).
- As always, begin to look at the /RESET line (pin 40), to see if it goes from low to high after more than 100 ms (which is the minimum allowed 'trc' value) once the power rail reaches at least 4.75VDC . In case of issue, check the CD4027.
- Check at startup once the reset condition has been released if there's some toggling on E clock (pin 37)
- Check at startup once the reset condition has been released if there's some toggling on the address lines (pins 9-25) and data (pins 26-33) lines.
- In the negative, read the address. Is it $FFFE or $FFFF ? In the affirmative, the µP is stuck at the reset vector, meaning it is unable to read from external memory.
- Also check the logic level of pins R/W (pin 34), /IRQ (pin 4) and /NMI (pin 6).


Power supply assembly check
As far as possible, it's safer to test the power supply on electronic loads or simply power resistors.
You need to drive the 'Inhibit' signal to activate the +15, -15 & 5.2VDC rails that supply the RF and analog boards. The ground of these rails is tied to the chassis/enclosure.
The 5.2VDC power supply for the CPU board and front panel is floating (its ground is not connected to the chassis).

Once you are confident with the behaviour of the RF/analog boards, consider replacing all of the capacitors in the power supply assembly. They are quite 40 years old.

[PerArdua]

Thank you time and frequency, good news is I'm better and ready for more excitement with the Adret.

I had to wait a little bit as I was actually sent an incorrect IC... All the ICs listed as broken above are now replaced. I am about 98% sure the glue logic is functional, however when taken out of the instrument the CPU is still stuck. (Note the picture I shared above was how I received the PCB, before applying any power I spent quite some time washing and cleaning the PCB. Unfortunately most traces around the battery had to be replaced with wire and UV soldermask, but I am confident in the physical repair).

At the moment the !RESET is held low constantly -  have tested the 4027 out of circuit in a test breadboard and it appears to work fine. Looking around the circuitry for the 4027 I notice that the VMI pin rises to about 1-2V - could this be part of the issue? The 4 input NAND (SN6) is outputting a HIGH, with pins 1 = HIGH, 2 = ~1V, 4 = LOW, 5 = LOW. Pin 2 is connected to VMA of the 6802 - I'm not sure if this could indicate a broken 6802 if it is not confident in a valid memory address. Pin 1 derives from SN5, which outputs almost exactly as you'd expect except for ~1V on the output of pin 7. As this connects up to SN18 RAM, could this be causing an issue?

In terms of address on the CPU - pin 18 (A9) ad a couple of others reading a strange voltage around 1.5V. Could this be indicative of a damaged CPU?

For the power supply, when you say drive the inhibit, do you mean the Valid (0) Enable pin and/or the presence alim (1) line detector? If so what should I drive them to?

Thanks again as always.

[timeandfrequency]

Hi PerArdua,

Great that you actually could clean-up the board and repair the missing tracks.


>"!RESET is held low constantly"
As long as the /RESET line is asserted, the CPU won't start. And for a CPU, the /RESET pin is the first and unique signal being considered before doing anything else (like reading the /NMI pin).
Following the /RESET line shows that this signal is provided by the CD4027 pin 1 and is used by the µP (6802), the GPIB controller (68448) and the 6821 PIA.
So the issue is around/before the CD4027. You are right when saying that it is interlinked with /NMI (Non Maskable Interrupt), but this pin will be considered by the CPU after the /RESET condition is removed.

Manage the /RESET and /NMI lines manually
So I would suggest you to act as follows :
- Switch off the lab PS.
- Remove the CD4027 from its socket, we do not need it for the moment.
- Connect the /NMI pin (= 'PA' = 'Presence Alimentation' = 'power supply is provided') to 5VDC
- Connect a 1 to 10 k resistor from 5VDC to /RESET
- Connect a small momentary switch from /RESET to GND.
- Activate and hold the switch (so /RESET = 0VDC)
- Set the lab PS to ON.
- Release the reset switch and look with your scope or logic analyser if something begins to toggle on the adress and data bus. It might be a very short event (<< 1ms) but this would give a hint about the CPUs health.
If the CPU is live, try to connect the front panel to the CPU board : perhaps the  7-segments displays will show some values.

Control lines between CPU board and PS assembly
'PA' = 'Presence Alimentation' = 'power supply is provided' is a signal generated by the power supply assembly and sent to the CPU board. It indicates that the 5.2VDC digital rail is stable and that the µP can start working. As it is tied to /NMI, I would say that 'PA' = 5VDC indicates that the power supply for the CPU board is OK.
The 'Inhibit' signal is an output provided by the CPU board which is sent to the PS assembly in order to activate the +15, -15 & 5.2VDC rails that supply the RF and analog boards. When 'Inhibit' is tied to 0VDC, the PS rails towards the RF & analog section are not active.

Read the EPROM contents
I would say that one of the next step could be to read/backup the EPROMS. So you will be able to check if there's still a readable program stored inside and also read the adress stored in the reset vector ($SFFE & $FFFF). The CPU has to jump to the adress stored in the reset vector just after the /RESET condition is released. This starting address should be between $C000 & $FFFD.

[UPDATE #1: added the paragraph below]

SN6 glue logic and weird VMA signal
For the moment, I do not really understand the function of SN6 pin 6 and why a combination of VMA (Valid Memory Adress) with other signals is rerouted towards the CD4027 and generates a reset condition. I'll have to RTFM to see if there's some information on that topic
Mmmh ! Perhaps the table below SN6 gives a hint : does this mean that accessing to an adress in the range between $1000 and $17FF actually fires a reset ?
 
Reading ~1VDC at the VMA pin is a bit weird. The 6802 manual cleary states that VMA is not a three-state signal.
So perhaps this will become a valid TTL level signal (< 0,8VDC or > 2VDC) once the CPU gets out of the reset condition, or there's a chip tied to that line that has a damaged input port or the CPU is ill.

[UPDATE #2]
Unfortunately, the SM is silent about SN6, which is not even shown at the CPU board bloc diagram.
.

[PerArdua]

Thank you for the clarification timeandfrequency.

Given that the CPU PCB has been cleaned up, and fresh glue logic installed, I feel slightly more confident with returning into the instrument. It is clear that the whole instrument is very interlinked. As mentioned previously, maybe the CPU is waiting for some other signal before continuing.

As such I decided it was perhaps best to ensure the power supply was functioning correctly. Reading the schematic (I attached a couple I have put together and resized to fit a single image), I realise the "inhibit (CPU schematic)/Enable (PSU schematic)" should actually be shorted to the floating GND - annoyingly called -5V on the PSU schematic - to turn on non standby voltages. As below:

Inhibit/Enable HIGH/floating:

+15V pilot ---- ON  (makes sense to keep the OCXO warm)
+15V ---------  OFF
-15V ---------- OFF
+5V ----------- OFF
floating +5V -- OFF
Dig_P +5V ---- ON  (referred to as 5P on CPU schematic)

Shorting inhibit/enable to floating GND (marked as -5V on the PSU schematic) turns everything ON.

It's an interesting PSU schematic and nice to refresh a bit of knowledge on differential amplifiers, however it's apparent to me that Adret perhaps didn't have the most cohesive nomenclature/artstyle guidelines as there are numerous differences between different schematics that make understanding the system more difficult. 3 years does separate the drawings though...

I don't believe Adret included the part numbers for the PSU motherboard components. These are (noting they use Qx and SNx multiple times on the same artwork) :

Q1 - 2N3772
Q2 - 2N3772
SN1 - LM337K
SN2 - LM350K

All supplies are within +-200mV, I will look to carefully adjust the feedback potentiometers tomorrow to bring them in a bit tighter - though this is with no load. Thus far it's been left running with no load for 20 minutes and no funny business, therefor I'm confident in hooking this up with some new ribbon cable.

I'll spend tomorrow working towards reading the ROMs. I thought I would have a go with using an Arduino to read them as the EPROM reader was a bit more expensive than I was anticipating.

All the best,

[George Edmonds]

Hi Per Ardua

Sorry for the delay in replying to you, I had kidney surgery in December last year and am still recovering from it.

In the past I have repaired a number of Adret 700 series instruments, both for normal failures and for leaking Ni-Cad batteries.

I know that you are probably well aware that the material that leaks from the Ni-Cad is both highly corrosive and conductive.  You can bet that although you did not power the instrument up the previous owner/s undoubtedly did causing allsorts of consequential damage.  I have in the past successfully repaired one with about the same level of contamination of the CPU board that your photograph shows.

Following the removal of the Ni-Cad battery I treated the board by brushing on to it white wine vinegar, the contamination is strongly alkaline so I used a mild acid to neutralise it, could also have used Citric acid, but I had none to hand at the time.  I then washed the board multiple time with a strong surfactant and IPA, finally rinsing the board with deionised water.  What I did find when I started to test the CPU board was that the contamination had not been removed from under the line of IC’s that go across the board, I had to replace them all using turned pin IC sockets.  There was also some damaged track work that had to be repaired using kynar insulated wire.  The real worry was that the contamination had managed to get under conformal coating and was starting to eat away the track work.  I do know that this repair lasted for at least two years after which time the instrument was sold on , to whom I do not know and I lost track of it.

As to the power supplies, the designer should have been sent back to do basic electronics 101 all over again.  Originally the diode used were 5401, would have died like May flies, then 5404 which would also have failed due to over current from the inrush current to the large electrolytic capacitors they were feeding.  I called the main power supply electrolytic capacitors, pink ones of unknown manufacture, used “magic capacitors” they used to go to zero capacitance due to no electrolyte in them , but where the electrolyte went was magic, there was no sign of it anywhere in the instrument, it just disappeared.

To then use harmonica style connectors to link the PSU to the motherboard was the height of stupidity.  Good plan if you want to constantly get burnt connectors, every 700 series instrument I have seen has had burnt power supply to motherboard connectors.

Now you asked a question regarding EPROM’s and EEPROM’s.  Now these comments are not Adret specific, but apply to most computer controlled signal generators.

Normally the instruments operating firmware is held in EPROM’s up until say the 1990’s when flash memory started to be used.  EEPROM’a or EAROM’s are normally used to hold the instruments calibration constants, passwords and instrument serial number etcetera which are unique to that one instrument.

There are two problems with EEPROM’s, they have a maximum number of write cycles before they fail and by far more importantly they need write protection while the supply rails stabilise and from drooping supply rails  The standard way of doing this is to monitor the +5V supply, if it is not correct the CPU reset pin is asserted to hold the CPU in a continuous state of reset thus preventing any false writes to the EEPROM.

For the above reason alone I suspect that the CPU board will not operate outside of the main instrument.

The use of decidedly none standard and unobtainable connectors for the CPU and other PCB’s is a real PITA.  I was never able to find any to make a PCB extender.  Hopefully someone may know a source of them.

I do have a Marconi-Adret branded instrument which probably has a copy of the last firmware used, it is version 742.0013 for the EPROM’s and 742A-0015 for the EEPROM.  There is also a second CPU board with EPROM’s version 7.1.88, the EEPROM has no version number, but is a 2816A.

It has taken me some time to write this posting so other events may have taken over in the meantime.

Hope the information helps and that you do finally get the signal generator working again.

G Edmonds

[PerArdua]

Thank you George,

I hope you are recovering well from your surgery, thank you for taking the time and energy to help with my repair.

I am, perhaps naively, optimistic about repairing this - even if I might need to see about getting a replacement PCB made up, it will all be an interesting learning experience. I am still (kind of) fresh out of university, trying to better my limited knowledge with real world examples. To that end, this repair has already been more useful than the more simple dried capacitor/broken op amp I've dealt with in previous repairs.

In terms of mitigating the effects of inrush current on the diodes, what design differences could/should have been made? I can imagine using a NTC thermistor or a relay to switch in/out a low resistance series resistor was within the realms of possibility in the early 80s - were these prohibitively expensive during that time?

Regarding the custom connectors, I've found that standard 0.1" pitch headers fit, providing you pull out/cut every other connection to permit mechanical clearance. This works for both male and female connectors, though perhaps there is some risk of overly large male headers damaging the female Adret connectors. I've drawn up some plans for an extender based on using these modified headers, if I need to purchase them later in the repair I'd be happy to send a spare PCB to you for free.

[timeandfrequency]

Hi everybody,

The use of decidedly none standard and unobtainable connectors for the CPU and other PCB’s is a real PITA.  I was never able to find any to make a PCB extender.  Hopefully someone may know a source of them.

I just had a quick look to the CPU board picture taken by PerArdua in an earlier post.
IMHO, the CPU board simply uses a vanilla 31 pins connector which can be purchased off-the-shelf from many common vendors.
These connectors were commonly used in (now vintage) TE.

I even managed to dig up an extender and some additionnal connectors from my storage barn (just need to remove the two plastic brackets to make it usable) .
And it seems rather easy to duplicate this part : drawing the artwork, manufacturing the PCB at PCBWay or JLCPCB, buying two connectors and a bunch of test pins to cobble such an extender should be doable for less than 20 bucks.


[UPDATE #1]

Inhibit/Enable HIGH/floating:

+15V pilot ---- ON  (makes sense to keep the OCXO warm)
+15V ---------  OFF
-15V ---------- OFF
+5V ----------- OFF
floating +5V -- OFF
Dig_P +5V ---- ON  (referred to as 5P on CPU schematic)

Shorting inhibit/enable to floating GND (marked as -5V on the PSU schematic) turns everything ON.

Great! The test you made matches with the text explanation provided in then SM. I did not dig into the PS schematics yet.


[UPDATE #2]

In terms of mitigating the effects of inrush current on the diodes, what design differences could/should have been made? I can imagine using a NTC thermistor or a relay to switch in/out a low resistance series resistor was within the realms of possibility in the early 80s - were these prohibitively expensive during that time?

1N5401 & 1N5404 have a maximum peak foward allowed surge currect of 200A, which is not that bad.

Even I did not verify, I guess that Siemens (later Epcos, now TDK) already sold power NTC's and PTC's to mitigate surge currents in the early 80', but I would say that such kind of parts were not commonnly used in 50/60 Hz transformer PS.
I've no idea if there where expensive at that time.

Furthermore, it's not trivial to choose the best suited power NTC or PTC to fit inside a PS. It depends on the transformer & electrolytics caracterstics and also the shape of the inrush current you want to obtain (not too steep, not too flat). Sometimes, it's easier to buy a bunch of different values and give it a try...

If you really want to dig into that topic, you may check out these links :
https://www.ametherm.com/inrush-current/inrush-current-faq.html
https://www.ametherm.com/inrush-current/ptc-thermistors-for-inrush-current-limiting
https://www.ametherm.com/ptc-thermistors-vs-ntc-thermistors-for-inrush-current
https://www.ametherm.com/inrush-current/calculators


If you are concerned with the limited inrush current of the legacy parts inside the Adret, choosing diodes with better features can also be an acceptable solution. This TO220 package, 2x5A, 150V diode has a maximum allowed peak inrush current of 620A. Even if you recap your PS with first tier electrolytics, 620A won't be reached. 

[George Edmonds]

Hi

I must disagree, we are talking about the CPU card to motherboard connector NOT the standard IDC connectors on the CPU board.

The CPU card to motherboard connector I have never seen used elsewhere in my sixty years of experience.  The parts list gives the manufacturer as Trelec, model TM31,  When I last checked about three years ago this manufacturer was still in business, but no longer supplied the type of connectors used in the Adret 700 series instruments.

It may well be possible to make up a suitable connector, BUT the pin and socket diameter are crucial if damage to the existing connects is to be avoided and good connections made.

G Edmonds