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| Understanding and Repairing Clock Generator on Adret 742A UHF Generator |
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| PerArdua:
Thank you George for the pointers and measurements, especially of T3. Apologies for my delay in replying, I have been away at a funeral, and not been well this week. :-[ A short update follows to show I am still (slowly) working on this. I have powered up the PCB (external of the instrument, not connected to anything other than a bench power supply) and observe a good 4MHz clock on the 6802, however the amber "busy" light does not illuminate. This is tied to the bus available pin of the 6802, such that it is not illuminated when either the !HALT input is in the low state, or the 6802 is a WAIT state as a result of executing a WAIT instruction. On the 742A CPU PCB, the !HALT input is tied to 5V through a 4.7k pull up resistor - I will measure this pin in the next day or two when I feel well. The rest of the CPU pins are in a steady state, so I am reasonably sure that nothing is happening. I am currently working my way through testing each (logic) IC on the PCB, as best as I can (testing the memory is impossible without a known good dump to compare it with). In either case, I will hopefully have a reader/programmer at the end of the month and will upload what I find. Thanks again to everyone who has helped. :-+ |
| PerArdua:
An update on my progress: I've tested every IC out of circuit (at least, those that can easily be tested such as buffers, flip flops, gates, etc), and have had some mixed results. The image below shows the results - red X indicates damaged IC, green O indicates a functioning IC, orange ? indicates an IC I am unable to easily test, blue / indicates ICs for GPIB connectivity (not worried about that yet). Clearly, the ICs around and below the battery are most likely to be damaged - this leaves me feeling a bit 50/50 on the state of the 6800 CPU, ROM, and the 6821 PIA. The damaged ICs are: SN05 - 74LS156N - Dual 2 line to 4 line decoder (in the 742A, configured as a 1 to 8 demux) SN06 - 74LS20N - Dual 4 input NAND gates SN07 - 74LS00N - Quad 2 input NAND gates SN29 - 74LS374N - Octal D type flip flops Plus SN01 and SN02 from the clock circuit, but those were identified as damaged earlier. My plan is to have a look over the rest of the instrument for any obviously damaged components, ensure the power supply outputs the correct voltages etc, and then make a digikey/mouser order to gain new parts. I know for certain the ribbon cables used to jumper the power supply output to the motherboard have been severed (a poor design choice imo), so I will attempt a fix on those after proving the power supply works safely. At that point I will try testing the CPU card again with the new ICs and hopefully see some life. At the end of the month I will also look to purchase a TL866ii plus EPROM reader/programmer - at that point I will be able to at least read the two EPROMs and the EEPROM. Any idea why they might have used the two types of memory? All the best. |
| timeandfrequency:
Hi PerArdua, Sorry to hear about your predicament, and I wish you to recover soon. CPU board repair Electrolyte leaking seems to have been significant and killed many IC's. Before inserting new ICs, I suggest to clean the board thoroughly by applying the process already explained above. CPU behaviour I've no knowlege on how the 6802 behaves in a 742A, but, as this gear was designed in the early 80', it shoudn't be deadly complicated. And we don't know either if the CPU board is able to run outside of the unit. Yet, it's better to make some probing while the CPU board is standalone. After initialization, maybe the whole programming scheme is event driven, just wating for an interrupt to occur on the /IRQ pin, which is tied to the GPIB controller (68448) and the 6821 PIA. The latter communicates with the front panel. A few hints to check the 6802 (after replacing all of the dead glue logic parts) - Check if the power supply rail is a clean 5VDC ±5 % (this should be OK thanks to the lab PS, but a nasty high frequency toggling burden can hinder the whole board). - As always, begin to look at the /RESET line (pin 40), to see if it goes from low to high after more than 100 ms (which is the minimum allowed 'trc' value) once the power rail reaches at least 4.75VDC . In case of issue, check the CD4027. - Check at startup once the reset condition has been released if there's some toggling on E clock (pin 37) - Check at startup once the reset condition has been released if there's some toggling on the address lines (pins 9-25) and data (pins 26-33) lines. - In the negative, read the address. Is it $FFFE or $FFFF ? In the affirmative, the µP is stuck at the reset vector, meaning it is unable to read from external memory. - Also check the logic level of pins R/W (pin 34), /IRQ (pin 4) and /NMI (pin 6). Power supply assembly check As far as possible, it's safer to test the power supply on electronic loads or simply power resistors. You need to drive the 'Inhibit' signal to activate the +15, -15 & 5.2VDC rails that supply the RF and analog boards. The ground of these rails is tied to the chassis/enclosure. The 5.2VDC power supply for the CPU board and front panel is floating (its ground is not connected to the chassis). Once you are confident with the behaviour of the RF/analog boards, consider replacing all of the capacitors in the power supply assembly. They are quite 40 years old. |
| PerArdua:
Thank you time and frequency, good news is I'm better and ready for more excitement with the Adret. :) I had to wait a little bit as I was actually sent an incorrect IC... All the ICs listed as broken above are now replaced. I am about 98% sure the glue logic is functional, however when taken out of the instrument the CPU is still stuck. (Note the picture I shared above was how I received the PCB, before applying any power I spent quite some time washing and cleaning the PCB. Unfortunately most traces around the battery had to be replaced with wire and UV soldermask, but I am confident in the physical repair). At the moment the !RESET is held low constantly - have tested the 4027 out of circuit in a test breadboard and it appears to work fine. Looking around the circuitry for the 4027 I notice that the VMI pin rises to about 1-2V - could this be part of the issue? The 4 input NAND (SN6) is outputting a HIGH, with pins 1 = HIGH, 2 = ~1V, 4 = LOW, 5 = LOW. Pin 2 is connected to VMA of the 6802 - I'm not sure if this could indicate a broken 6802 if it is not confident in a valid memory address. Pin 1 derives from SN5, which outputs almost exactly as you'd expect except for ~1V on the output of pin 7. As this connects up to SN18 RAM, could this be causing an issue? In terms of address on the CPU - pin 18 (A9) ad a couple of others reading a strange voltage around 1.5V. Could this be indicative of a damaged CPU? For the power supply, when you say drive the inhibit, do you mean the Valid (0) Enable pin and/or the presence alim (1) line detector? If so what should I drive them to? Thanks again as always. |
| timeandfrequency:
Hi PerArdua, Great that you actually could clean-up the board and repair the missing tracks. >"!RESET is held low constantly" As long as the /RESET line is asserted, the CPU won't start. And for a CPU, the /RESET pin is the first and unique signal being considered before doing anything else (like reading the /NMI pin). Following the /RESET line shows that this signal is provided by the CD4027 pin 1 and is used by the µP (6802), the GPIB controller (68448) and the 6821 PIA. So the issue is around/before the CD4027. You are right when saying that it is interlinked with /NMI (Non Maskable Interrupt), but this pin will be considered by the CPU after the /RESET condition is removed. Manage the /RESET and /NMI lines manually So I would suggest you to act as follows : - Switch off the lab PS. - Remove the CD4027 from its socket, we do not need it for the moment. - Connect the /NMI pin (= 'PA' = 'Presence Alimentation' = 'power supply is provided') to 5VDC - Connect a 1 to 10 k resistor from 5VDC to /RESET - Connect a small momentary switch from /RESET to GND. - Activate and hold the switch (so /RESET = 0VDC) - Set the lab PS to ON. - Release the reset switch and look with your scope or logic analyser if something begins to toggle on the adress and data bus. It might be a very short event (<< 1ms) but this would give a hint about the CPUs health. If the CPU is live, try to connect the front panel to the CPU board : perhaps the 7-segments displays will show some values. Control lines between CPU board and PS assembly 'PA' = 'Presence Alimentation' = 'power supply is provided' is a signal generated by the power supply assembly and sent to the CPU board. It indicates that the 5.2VDC digital rail is stable and that the µP can start working. As it is tied to /NMI, I would say that 'PA' = 5VDC indicates that the power supply for the CPU board is OK. The 'Inhibit' signal is an output provided by the CPU board which is sent to the PS assembly in order to activate the +15, -15 & 5.2VDC rails that supply the RF and analog boards. When 'Inhibit' is tied to 0VDC, the PS rails towards the RF & analog section are not active. Read the EPROM contents I would say that one of the next step could be to read/backup the EPROMS. So you will be able to check if there's still a readable program stored inside and also read the adress stored in the reset vector ($SFFE & $FFFF). The CPU has to jump to the adress stored in the reset vector just after the /RESET condition is released. This starting address should be between $C000 & $FFFD. [UPDATE #1: added the paragraph below] SN6 glue logic and weird VMA signal For the moment, I do not really understand the function of SN6 pin 6 and why a combination of VMA (Valid Memory Adress) with other signals is rerouted towards the CD4027 and generates a reset condition. I'll have to RTFM to see if there's some information on that topic Mmmh ! Perhaps the table below SN6 gives a hint : does this mean that accessing to an adress in the range between $1000 and $17FF actually fires a reset ? Reading ~1VDC at the VMA pin is a bit weird. The 6802 manual cleary states that VMA is not a three-state signal. So perhaps this will become a valid TTL level signal (< 0,8VDC or > 2VDC) once the CPU gets out of the reset condition, or there's a chip tied to that line that has a damaged input port or the CPU is ill. [UPDATE #2] Unfortunately, the SM is silent about SN6, which is not even shown at the CPU board bloc diagram. . |
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