Electronics > Repair
Understanding and Repairing Clock Generator on Adret 742A UHF Generator
PerArdua:
Hi,
I'm currently attempting a repair of an Adret 742A UHF Generator. I've identified a number of issues, not limited to numerous blown capacitors, broken ICs, significant damage from a leaked NiMh battery pack, etc. At this stage I have repaired the damage to the CPU PCB caused by the battery leak, and verified correct connections etc. As part of testing, I am trying to create a sensible looking CPU EXTAL signal by powering just the system OCXO and CPU clock generator portion of the CPU PCB external from the instrument.
The schematic for the CPU PCB can be found on pages 17 and 18 here: http://ftb.ko4bb.com/manuals/188.222.43.3/ADRET_742M1_RF_Generator_Service_Manual.pdf with PCB layout and component list on the following pages.
The clock circuit unfortunately lies over two separate pages, for convenience I have attached a joined up and streamlined version of the clock circuit below.
I have ascertained that a 10 MHz signal from the OCXO enters the CPU bord through pins 15 and 17 of the CPU board's main connector (bottom of page 18). It is then converted into a single-ended signal before being buffered/inverted by a 74LS04N before clocking a 74LS196N ripple counter. This counter effectively performs a division by 2.5 on the 10 MHz signal, producing asignal that is periodic over three non periodic pulses. This signal is the filtered by an LC bandpass filter with a centre tapped transformer (T3). This filter is somewhat tunable as T3 is inside a metal can with a tuneable ferrite cap. The output signal is buffered again by Q3 and inverted by the 74LS04. This should produce a 4 MHz EXTAL signal for the 6802 CPU.
Unfortunately, the battery leak had completely destroyed the windings of T3. The components list simply lists T3 as a 15+2x7 turns F10B transformer. I have assumed this means 7 turns either side of the centre tap, and 15 turns on the single side. I rewound the transformer in a relatively neat job and managed to assemble it into the can without too much issue.
During my initial tests, I found both the 74LS04N and 74LS196N ICs were faulty. Replacing them with new parts (I have replaced all components with new versions, excluding T2 which survived unscathed) sourced from a reputable dealer (though I could only find a 74LS196CP) seems to have restored proper functionality of those portions of the circuit. However, the EXTAL signal appeared to be of dismal quality - see image below, obtained whilst measuring the EXTAL net of the 6802, with 6802 removed from the PCB. The 6802 datasheet (https://www.jameco.com/Jameco/Products/ProdDS/43502.pdf page 3) suggests that Vhigh-min would be 2V - clearly this runs the risk of incorrectly clocking the 6802.
I removed T3 from the circuit and measured the inductance of each winding. both of the tapped windings were identical, between 1.0uH to 1.5uH with the ferrite cap fully screwed in. The single side winding measured between 3.4uH to 5.3uH. I used these values in a SPICE simulation (attached, along with a CSV file and plot of a measurement from the output of the 74LS196 being used as the PWL for the voltage source), and found that ideally (assuming 1:2 turns ratio) these values should be around 2.4uH and 4.8uH. I could try rewinding these, but I'm conscious of damaging the old plastic winding loom, and also of not being able to do much better than my first attempt (which was, as far as I'm concerned, pretty neat). As such, I elected to add more capacitance to C5 and C6, effectively lower the centre frequency and narrowing the pass band of the filter. However, the effect on the output was negligible.
I am at a stage where I feel that whilst I understand what the circuit is trying to achieve, I'm not sure I get the 'why' or 'how'. I am thinking there might be some system synchronisation that requires the derivation of the CPU clock from the main system OCXO, rather than using a standalone XTAL - what that is though, I have no idea. unfortunately all documentation is in French and extremely hard to come by. I have only found a small handful of mentions of this instrument on the internet. Secondly, I am not sure as to what signal is 'sufficient' - I cannot see it producing a periodic 4 MHz signal (rather a 4Mhz signal averaged over some time period), but in that case - why filter the output from the 196? Why not feed directly the 6802 from the 196? At this stage, I am considering using the output from T3 (Q3 base - below) to drive a high speed comparator with hysteresis to produce a clean EXTAL signal, but then this wouldn't be much different from using the 196 output directly.
I'm a bit confused as to what next step I should take, and open the floor to suggestions and interpretations of the circuit. I do not want to give up on this instrument, and happy to try some alterations (adding a 4 Mhz XTAL, or comparator or whatever), but would like to seek some guidance before I chase too many rabbit holes. :)
timeandfrequency:
Hi PerArdua,
--- Quote from: PerArdua on January 08, 2023, 04:36:59 pm ---
[...]I am at a stage where I feel that whilst I understand what the circuit is trying to achieve, I'm not sure I get the 'why' or 'how'. I am thinking there might be some system synchronisation that requires the derivation of the CPU clock from the main system OCXO, rather than using a standalone XTAL - what that is though, I have no idea.[...]
--- End quote ---
The ADRET 74X Series of RF Generators are build around multiple 'interwinded' PLL loops and the constrain of synchronysing EXTAL with the 10MHz reference clock is a legitimate question.
By the way, fully understanding all of the tricks packed inside ADRET T&M stuff instantaneousy pushes you to the 'electronic guru' level. Every second ADRET equipement was a masterpiece and providing explanations and details on how or why is was done that way was not among their mindset. All of the bloc diagrams and schematics are provided, but explanations are sparse. Reparing such a stuff can be a long way to go.
I had a quick look to the CPU board to get a ballpark of its block diagram and also to some other boards where the CPU has to poke in, like the 'Analog board' #0277490000 and the 'Eighty steps board' #0277500000.
One can see that the CPU sets values for CNAs, loop dividers and signal flow registers, but I could not spontaneously identify a synchronization constrain. The CPU updates the registers inside the IC's, writes digital values inside the CNAs, but it seems that this can be done at any time. Once update is done, the numerous PLL loops just lock in using the new divider values, signal path is routed according to the relevant frequency band and mixing scheme and finally the output signal just shows up with correct frequency, level, modulation mode, modulation frequency and modulation depth.
-> So I would definitely give it a try with a vanilla 4 MHz TTL oscillator or even a 4 MHz crystal plus two 18pF caps (and also using the XTAL pin).
Why did the ADRET engineers extract the EXTAL signal from the OCXO signal ?
Well, it's a demanding question and the documentation is silent on such matters, so I only have some clues :
- These boat anchors were forged with utmost attention in limiting non-hamonics, sub-harmonics, phase noise and other spurious signals. Synchronysing every internal clock to a master clock probably contributes to maintain those specs at the highest possible level.
- If there's no master clock (internal or external 10MHz), the µC is halted or at least stuck : this also means that any GPIB communication is denied. If this gear is used in an automated test bench, hindering the GPIB data exchange is a strong manner to tell the GPIB Master that something's going wrong with the RF Generator...
Now, if you prefer not alter the existing circuit and try to make it work as is, here are some hints :
- The hex inverter plus Q3 is more or less used as an analog amplifier pushed into saturation, perhaps with some hysteresis (positive feedback via R11). It's always a bit tedious to adjust the polarization when using logic gates this way. Furthermore, you said you replaced the hex inverter with a new one, which might be internally slighty different to the legacy one.
On your *.asc simulation schematic (nice work !), you put the labels at the correct location where to set the scope probes into the real circuit : at first you might need to maximise the filter output's level (to center it on the 4MHz frequency) and then check at the input of the logic inverter for acceptable signal levels. It's important to avoid as far as possible to have the high and low peak values of the sine signal inside the 'undefined region' : TTL has the input high level above 2.0 V and the input low level below 0.8 V. So try to fiddle R9, R10 and R11 (± 2 steps of E12 resistor series values) to get the best possible signal at the logic gate input (= well below 0.8V and well above 2V). Use your simulation tool to find which way to act (increase or decrease the resistance values). I also noticed in your simulation file that the modeling of the inverter's behaviour might not be very faithful : the output signal state change at very high input voltage levels. Fortunately, that's not that important for the circuit health : focus your attention onto the input signal of the logic inverter. Once you have at the input at least a nice sinewave with adequate levels (or even a quite rectangular signal), the ouput shall be fine.
- If the input signal at the logic gate is too weak, maybe that Q3 lacks of gain and needs to be replaced. Prefer using a BC560C ('C' = highest values of hfe, typically 500 @ Ic=2mA)
- Another drawback of feeding a TTL logic input with a 'not square' wave (e.g. sinewave) is its low voltage rate of change which tents to push the gate into a metatstable state. Try to replace your 74LS04N with a 74LS14 which provides the same logic function, same pinout, but with Schmitt-trigger inputs that much better cope with 'slow' changing signals.
[update 1] : corrected the URLs towards the 742 SM pages
PerArdua:
Hi timeandfrequency,
Thank you so much for you in depth reply - I really appreciate it. In all honesty, i am not sure if this machine is the product of beauty or madness, but that is perhaps more a result of my not being a grey-beard!
I will try with a crystal and two caps, and will see about trying to get the instrument to boot. There are plenty of blown tantalum capacitors on the +15V rail of this instrument - it has had a hard life for sure, but I hope it can return to operation. At that point I may try to get it working with the original circuit, and will try to produce a card extender to allow me to measure and adjust during operation as a system. I will offer a free card extender (I might even offer to pay postage) to someone willing to make some measurements on a good 74X CPU board. :)
I also intend to purchase a EPROM reader/programmer for the 3 EPROMS (2x CPU Board, 1x in for the attenuator and UHF board) - hopefully they have not degraded, and their contents can be accessible to those attempting future repairs/investigations into these instruments. Do you (or anyone else) have any recommendations for a suitable reader/programmer for the D2764 EPROMs?
I suppose the designers of these instruments are no longer with us? It is a shame that so little documentation exists - at least which I have found from my searches - but maybe more exists on the French side of the internet (my ignorance, sorry).
Thanks again for your time and sharing your knowledge, I will look to attempt the crystal implementation next week and will report back.
timeandfrequency:
Hi PerArdua,
Thanks for your kind reply.
The guys at ADRET were truly top notch and could easily compare to their peers at HP, TEKTRONIX, GEC-MARCONI and FLUKE. Even if I have limited knowledge on that topic, I would say that the manufacturing quality was better at HP than at ADRET.
Maybe these links can help you to get more information about ADRET :
The Adret story (english translation)
Adret legacy/revival Internet pages (english translation)
About 15 years ago, I remember having setup with another guy a small test by using an ADRET 74X.
Step 1 : By using a really quiet 10MHz reference crystal (sine output), plot its spectrum around the carrier using a high end spectrum analyser (RBW was set to the narrowest available value that was 3 Hz). Even with a tiny frequency span, it takes long minutes to plot the spectrum.
Step 2 : Use this reference crystal as external clock for the 74X, set any frequency value (let's say 500 000 000 Hz), plug the output of the generator into the SA and draw the same spectrum around the 500 MHz carrier.
-> There was no difference between both traces : same shape ! No additional phase noise at the bottom of the carrier. Even with an 10 Hz output frequency resolution, which leads to very high division factors inside a PLL loop (that creates huge amount of jitter), the uncanny frequency addind and mixing scheme inside the 74X actually adds no phase noise. At the end of the seventies, this was a huge achievement. The 1976 ADRET catalog gives some clues about iterative frequency synthesis (see Fig 3). Similar behaviour/specs are now available when carefully using DDS ICs because they do not make use of dividers the same way than those required in PLL loops.
It is a really nice idea to save the EPROMs contents. I would suggest you to get in touch with KO4BB that would for sure appreciate to host the binary files on his Internet site. Please include also in your data package the model and serial number of your equipment.
Also be very careful with these old parts which - due to aging - become very sensitive to electrostatic discharges. So when reading the EPROMs, ground all equipment and wear at least an anti-static wrist strap.
Unfortunately, I have little knowledge about EPROM readers/programmers, but I'm pretty sure that other members on the forum are gurus in that realm and can provide you some clever advice.
For the CPU card revival, once the µC clock is neat, try to power it up (via a lab PS with current limitation), and perhaps also connected to the front panel. Then, by probing both adress an data buses, check for lines that never toggle, which could be a clue for a dead part or a short to GND/VCC.
If you have the required gear, you may also try to communicate with the CPU via its GPIB interface. The message structure and commands are not that complicated (have a look at the bottom of the page).
I will also try to follow your next posts on this adventure.
DLJ:
Hi PerArdua.
You are correct with the details of the LS196. It divides the 10MHz clock down to 4MHz for the CPU, though it is slightly asymetric, as you noticed.
One little detail that you might have missed is the "rouge - NO clock" led D1, if this is off then you have a running clock. If it is lit then you have problems :)
There is also an orange "error" led which should stay off, mine flashes occasionally, but that is becasue my Adret is currently faulty :(
If your EPROMS are 2764 then you will have difficulty finding a programmer that can supply the 21V needed for programming, although reading the data should be fine with alsmost any programmer. However 2764As seem to be supported by the cheap programmers.
I have attached some fresh clk waveforms, look the same as yours.
Hope that helps.
Dave
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