Hello, as it is known and experiment by different members, it is quite easy to upgrade via GPIB the SRAM acquisition A10 board from 1M or 2M options. Some of these A10 boards have already soldered the maximum SRAM storage memory so only by software we can manipulate or set which option: 50Ko standard or 500Ko (option 1M) or 8 Mo (option 2M).
However after inspecting 6 different TDSxxx wether C serie or D serie, I have two technical questions.
First here are the different SRAM models I've found so far within the TDS520D, TDS540C, TDS754D, TDS784C and TDS794D:
- AS7C164 (8K x 8bits) able to offer option 1M
- AS7C256 (32K x 8bits) but the two TDSxxx were set standard 50K
- IDT7124 (128K x 8 bits) able to offer option 2M
Question 1: do you know if the oscilloscope will fail or brick or self-detect an issue when forcing option 2M (8Mo) but the SRAM total memory is able only to offer 50Ko or 500Ko storage
Question 2: what is so particular with AS7C256 because I find strange the total memory (there are always 16 SRAMs per channel) offers 32K*16*4 = 2Mo
Does this AS7C256 internal mapping hardware can only work with 50Ko option even though its storage is higher or is it OK to set at 500K (option 1M) without failure ?
Thanks, Albert