Thank m k to stay with me in this madness.
After some emails, TTi support told me they believe/think the uP must be defective and that's it, they did not respond to my last email.... I let them go in peace...
They helped me a lot for free!
Despite that I think we have still cards to play, now that we know that it's an OVP problem we can dig into the right direction.
Please be aware, if you see a OVP malfunction in your device, I would say 90% the bad guy is the power board, my case is an unicorn IMHO.
According to my rev eng, there are 2 places where the output voltage (aka vsense+ and vsense-) comes into the control board:
1 - into the ADC
2 - into the VC generation analog part, basically to close the output voltage regulation feedback loop:
Vset ----> Vc --> Output ----
| |
--------------------------
- Vc is the control voltage
- Vset is the target voltage coming from the uP
Please note the Vset to Vc analog part is on the control board, the Vc to Output is on the power board.
Now, two facts:
a) I can't find any problem in the analog control board [CB] part
b) after powering up the unit, immediately the OVP is triggered on the side (master or slave does not matter) where the offending control board is installed.
Here below the startup sequence on the offending side

Green is the 5V rail
Blue is Vc
Yellow is Vset
this means to me:
1) Assuming the uP is still alive since I see "OUP tRIP" in the display, we need to check what it is going on between Vsenses lines before and after the ADC.
2) I need to compare the same startup sequence on the good side with output off, to see if Vc going to the roof for about 85ms after startup is normal.
I think this is not a problem... Vset stay at zero.... so...
[oh I did not check if the output is spiking at startup as well... but since Vset is 0 all the time, I do not expect any movement there.]
Before the ADC this is what is happening:

where A17 and A16 are the two ADC inputs, simulated in QSpice we get:

it's too late now, I need to sleep.... more to come.