ie: If the 5V rail goes down before the +15V rail does, then the "power stable" line will not deactivate in time to avoid the RAM being scrambled on power down.
Ok, I think this and previous posts is what I'm looking for.
The original 5v power supply has been replaced by a "home made" one on veroboard, other supplies are as per circuit diagram, and the Nicads are now 3 x AAA cells.
The Power Stable circuit appears to be working, but U33 seems to have not been fitted at factory, and Power stable is connected directly to pins 8/9 of U36, so the MREQ functionality designed originally is disabled. (According to the service manual, this was to prevent a valid memory write from being interrupted during power down)
But the point is, that after power down, the Z80 continues activity for around 22mSecs or so, but the Power Stable line continues high for 120mSec.
So if this situation is likely to corrupt the memory, then that is what is happening.
Over the last couple of days I have been investigating modifying the Power Stable circuit, to see if I could get it to shut down in less than 20 mSec, but the Power Stable circuit is too weird and unstable to mess around with, I have had to deal with this before.
It has megaohm resistors, and all this is 40 years old. (Scoping pin 14 of U63 is enough to stop it working)
It does though introduce a switch on delay on the _reset line as it is supposed to do.
So, if the problem is the replaced and poorly constructed 5v rail doesn't have enough capacity to outlast the Power Stable 120mSecs, then the problem is at least now clear.
Edit: It's actually just the 5v regulator circuit/Nicads that got replaced, but it does look a bit Mickey Mouse.
I'll check all the appropriate caps tomorrow, thanks for all the input.