Go on then - do it yourself. State the equations and assumptions and plug in the numbers. Prove I'm wrong. Write it up, you will have made your name and people will flock to your door, and you will be able to charge outrageous consulting fees. Seriously.
I did write a blog about signals and breadboards, but you haven't even read it. I guess if I write about ground bounces you won't read it neither

Hint1: tell us what do you think does happen with an LC circuit?
It is quite a bit in my blog on what I think happens in LC circuits on breadboards, with models, diagrams etc. It's not too late. You can click the link and read it.

That's an interesting graph. It is taken from 1988 TI application note ("Advanced CMOS logic
Designer's Handbook"), where they discuss the pin location DIP packages for their new HC series. They decided to relocate the power pins to the center of the chip. The picture above is the measurements with DIP package having power pins on the sides. When they have put the power pins into the middle, the effect has been alleviated and voltage spike became negligible.
TI certainly wanted to exaggerate the effect to show the advantages of their clever innovative pin placement. They drive 7 50 pF loads. The is equivalent of suddenly connecting 350 pF capacitor to the power rail. Voltage sagged 2V. Today, if this happened to me, I would say that it's either a bad power supply or inadequate bulk/bypass capacitors. Cannot relate to what it would mean in 1988, but anyway, the voltage sagged 2V.
Sane people don't drive capacitive loads directly. It's a good idea to add a series resistor, which limits current and completely eliminates the inrush effect. Thus, the effect of such magnitude cannot be observed in real circuits. This has nothing to do with breadboards, BTW.
Note that the PCB conditions are far better than you could find on a solderless breadboard.
In this particular case, the extra inductance of the signal wires would help. TI had the capacitive loads very close. If there was a foot of wire between the driver and the 50 pF load, none of this would happen. The inductance of the wire would limit the rate of current rise thus eliminating the magnitude of the inrush current. No way you can achieve super fast rise times when driving through long wires. Thus, there wouldn't be any inrush current in the first place.
Not only that. You should expect all the problems caused by too sharp driving to be alleviated by wire inductance in the breadboards. It simply doesn't have enough bandwidth to pass through very sharp pulses. When I was writing my blog, I wanted to find reasonable values of inductance and capacitance which would cause high frequency (500 MHz or so) oscillations, and I failed. I still published the picture of what I wanted to achieve, but the capacitance and inductance I used to model it were out of the range of what can be found in breadboards.