Electronics > RF, Microwave, Ham Radio

ADF4360-0 cannot lock

<< < (4/5) > >>

WOWOWOWOWO:
Hey, I encountered a new problem. When I used this chip for frequency sweeping, it had a frequency deviation of about 150M. What is the cause? |O

joeqsmith:
I showed my old scope in that video that I used to look at the output signals with.   I've used the devices for digital and run them at a fixed frequency.   I don't remember the parts having a sweep function.   Are you manually setting each frequency?  If so, I suspect something is wrong with the interface.  Not meeting timing, not meeting thresholds, edge rates........   

I still have that eval board and another test board that I could try out.   These I know the interface was done correctly and both are reliable.  If you would like me to try something to replicate what you are seeing, let me know. 

Bud:
This chip and fixed frequency PLLs are not suitable for sweeping. It can be done but as joeqsmith said timing has to be observed fot the PLL to lock after each step. Also the chip may produce all sort of artefacts between steps because of breaking the locked state. A way to minimize that is to turn the output off if the chip allows.

WOWOWOWOWO:
This is the case. I have used the official software to generate one N register value, which can be used to sweep 2.4G~2.5G. The value of N is changed every 1S. When I sweep three frequency points, it is This operation can be completed without frequency offset, but when I sweep 240 frequency points, a frequency offset of about 180M will occur. Is it because too much data causes an instantaneous impact on the output pins of the FPGA, causing interference?

WOWOWOWOWO:
As you said, but it can be done when three frequency points are scanned. :-BROKE

Navigation

[0] Message Index

[#] Next page

[*] Previous page

There was an error while thanking
Thanking...
Go to full version