ADF4360-0 cannot lock

[WOWOWOWOWO]

My phase detection frequency is 10KHZ, the output waveform of R DIVIDER OUTPUT is a pulse with a frequency of 10Khz, DVDD is vdd, and N DIVIDER OUTPUT is a pulse with a frequency close to 20KHZ. The output of LOCKDETECT is low. I don’t know where the problem is. , Please give me some advice,

[WOWOWOWOWO]

Now the voltage of CP is 0V

[joeqsmith]

You provide very little info.   Post your schematics, software interface and the simulation files. 
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Include a few pictures of the construction as well.

[WOWOWOWOWO]

ok，thanks.The schematic diagram quotes the classic example in the manual, and the red part uses the balun matching output in Figure 2, and the rest of the conditions are as mentioned above.
My phase detection frequency is 10KHZ, the output waveform of R DIVIDER OUTPUT is a pulse with a frequency of 10Khz, DVDD is vdd, and N DIVIDER OUTPUT is a pulse with a frequency close to 20KHZ. The output of LOCKDETECT is low.[attach=1][attach=1]

[WOWOWOWOWO]

Sorry for using the forum for the first time, I don’t know how to describe clearly

[joeqsmith]

Supply the snip-it of code that programs the device and if you have the simulation files that would help.  It's been a while since I have looked at the part but thought you could save the files.   

[WOWOWOWOWO]

Thank you very much for your attention to this issue. The following is the data and simulation diagram, where the interval between the C register and the N register is 5ms.

[WOWOWOWOWO]

I use FPGA control

[joeqsmith]

I wonder why you refuse to provide the file.    Oh well, I am sure you have your reasons.  Good luck. 

[WOWOWOWOWO]

sorry，The language barrier has caused a misunderstanding. If you are patient, please take a look,RF_LO.zip is sch,test.zip is ISE project.

[joeqsmith]

I am very lazy and start by entering my constraints into ADISim.  ADISim should prevent you from violating any of the component's constraints.   This software will create a schematic with component values along with how to program the device.  I also program the devices with an FPGA.   I've not had any problems with these parts.     

They used to offer evaluation boards.  You could modify one of these and make sure it meets your performance before committing to layout.  Remove the FPGA and layout from the problem. 

Not very helpful but here you can see the eval board with a -4.  I show the simulator as well.
https://youtu.be/4rJcEVj8OYo?t=124

For verifying your design, start with ADISim.

[WOWOWOWOWO]

Thank you very much. Now the LOCKDETECT test on my board is passed and the output is high, but there is still no signal output. There is a new program document below, some register parameters have been changed, and my simpll design, my circuit design and evaluation The version seems to be only a few decoupling capacitors different, will it cause a big impact?

[joeqsmith]

I would start with just the 2X 50ohm pullups and make sure the outputs toggle.   Do you have equipment that can look at it? 

My version of ADIsim is from 2005 and it looks like I need to register.  What version of the tools are you using?

[WOWOWOWOWO]

I used SIMPLL v5.40, which was recently downloaded from the ADI official website. When I changed to a classic circuit, the output waveform was still the same, but I found that the VTUNE pin voltage reached about 2.7V, which is abnormal.

[WOWOWOWOWO]

Haha , it has been solved. It turns out that the measuring instrument is not good. The measurement is very accurate after using the broadband receiver. But there is still a problem, how can I see the noise and frequency offset it produces. But thank you very much for your explanation,   :)谢谢

[WOWOWOWOWO]

Hey, I encountered a new problem. When I used this chip for frequency sweeping, it had a frequency deviation of about 150M. What is the cause?

[joeqsmith]

I showed my old scope in that video that I used to look at the output signals with.   I've used the devices for digital and run them at a fixed frequency.   I don't remember the parts having a sweep function.   Are you manually setting each frequency?  If so, I suspect something is wrong with the interface.  Not meeting timing, not meeting thresholds, edge rates........   

I still have that eval board and another test board that I could try out.   These I know the interface was done correctly and both are reliable.  If you would like me to try something to replicate what you are seeing, let me know. 

[Bud]

This chip and fixed frequency PLLs are not suitable for sweeping. It can be done but as joeqsmith said timing has to be observed fot the PLL to lock after each step. Also the chip may produce all sort of artefacts between steps because of breaking the locked state. A way to minimize that is to turn the output off if the chip allows.

[WOWOWOWOWO]

This is the case. I have used the official software to generate one N register value, which can be used to sweep 2.4G~2.5G. The value of N is changed every 1S. When I sweep three frequency points, it is This operation can be completed without frequency offset, but when I sweep 240 frequency points, a frequency offset of about 180M will occur. Is it because too much data causes an instantaneous impact on the output pins of the FPGA, causing interference?

[WOWOWOWOWO]

As you said, but it can be done when three frequency points are scanned.

[WOWOWOWOWO]

The frequency sweep problem has been solved. It turns out that the data I sent is wrong, but my power is very low. I don't know how to increase it. Is my PCB trace not matched to 50 ohms? And when I use 0.1s as the frequency sweep step time, the measurement occasionally produces a little noise. I do not know how to solve this.