Author Topic: Buffering the output of the SI5351A clock generator IC?  (Read 799 times)

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Offline profdc9

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Buffering the output of the SI5351A clock generator IC?
« on: November 19, 2019, 05:39:11 am »
When the SI5351A clock generator IC is generating two different frequencies, it seems that one frequency is present in the other signal at about -50 to -60 dB below the expected frequency.  I am thinking to use a buffer to reject the weak unwanted signal and possibly source the wanted signal at a lower impedance.  I was looking at clock distribution chips but they seem kind of overkill for this purpose.  Is there a cheap, common way to buffer a digital clock signal of perhaps up to 200 mhz frequency?
 

Offline OwO

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Re: Buffering the output of the SI5351A clock generator IC?
« Reply #1 on: November 19, 2019, 05:55:59 am »
Inverters can be used (e.g. 74LVC2G04 which can go up to 200MHz) but buffering the output won't necessarily get rid of the leakage because part of the leakage is through affecting phase (jitter of the rising and falling edges). I would probably just use a second si5351 if leakage was a problem.
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Offline radiolistener

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Re: Buffering the output of the SI5351A clock generator IC?
« Reply #2 on: November 19, 2019, 07:35:40 am »
profdc9, you cannot remove RF leakage between channels with buffers, because it happens inside chip.

if you want more isolation, then you're needs to use separate si5351 chips for each channel.

Buffering is not needed for si5351, because it already has enough power to drive low impedance load. You can connect 50-ohm load directly to si5351.

« Last Edit: November 19, 2019, 07:39:47 am by radiolistener »
 

Offline profdc9

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Re: Buffering the output of the SI5351A clock generator IC?
« Reply #3 on: November 20, 2019, 03:17:10 am »
I looked at this with a simulation, and the answer seems to depend on factors that I do not know.

For example, if the inverter acts like a nonlinear amplifier, then high frequency noise might get through and be amplified by the nonlinear response, because the high frequency components of the square wave will get through the inverter, and furthermore the nonlinear response will tend to mix the high frequency components of the weak and strong signals.  On the other hand, if the inverter acts more like a Schmitt trigger, it may not have the problem of being falsely triggered often, but Schmitt triggers seem to be too slow for this application.

In the simulation below, the first simulation is without the second weaker signal.  A lot of the ripple from the bandlimited square wave passes through the inverter and causes a lot of noise.  This gets even worse with the addition of the second weaker signal.  This model assumes the inverter has infinite bandwidth, and so will potentially amplify any small ripple of its input.

I would like to avoid another SI5351A as it would require another free running oscillator, and I would like to avoid slaving the oscillator crystal of one SI5351A off the other as it might be a path to conduct the other unwanted signal from one SI5351A to the other.  So while I agree that using the inverter is probably not a good idea, I am not sure how to prevent a two connected SI5351A from having the same problem as one.

Dan
 

Offline OwO

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Re: Buffering the output of the SI5351A clock generator IC?
« Reply #4 on: November 20, 2019, 04:29:49 am »
You can use the inverter to buffer the reference clock signal and drive the two si5351s. The leakage will be far lower because it has to travel through two si5351 rf to refclk paths, and the inverter buffer will reject leakage better because it is buffering a much lower frequency and so stays in the saturated (low impedance) region most of the time.
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Offline profdc9

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Re: Buffering the output of the SI5351A clock generator IC?
« Reply #5 on: November 20, 2019, 02:55:56 pm »
Ok, I think then I can use two SI5351A.  I have a VNA design which currently can achieve about -50 dB isolation between Port 1 and Port 2, however, I think that it could be better.  What's pretty cool is that I've knocked the minimum measurable reflection on S11 down to -65 dB at 1 to 200 MHz and -50 dB from 200 to 600 MHz, and hoping to obtain similar performance from S21. 
 

Offline radiolistener

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Re: Buffering the output of the SI5351A clock generator IC?
« Reply #6 on: November 20, 2019, 04:27:29 pm »
if you want better isolation between channels, you're needs to use two separate si5351 clocked with single oscillator.

with si5351A you will get the same result, because it has the same leakage between channels
 

Offline paul002

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Re: Buffering the output of the SI5351A clock generator IC?
« Reply #7 on: May 24, 2020, 02:48:41 pm »
The thread is a bit old but I have been experimenting to reduce the crosstalk and the radiolistner is right. Buffers will help a bit. But best is to have two separate si5351. I just stacked them and put the SDA and SCL to seperate ports on a ESP32. I only use one output on each si5351 and have a simple buffer a msp10 with 1k to the si5351 output collector to +3.3 V and emiter 47Ohm grounded use 100Nf to get output. Next I alsoi added some filters but that gave some strange effects. If you use a filter I had to add a 10db attenuator between filter and the buffer. I think this is because all unwanted frequencies are reflected back to the si5351 and generates spurs in your receiver. I am now making a pcb with all on it. 
 

Offline profdc9

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Re: Buffering the output of the SI5351A clock generator IC?
« Reply #8 on: May 24, 2020, 07:20:26 pm »
I ended up using two SI5351A, taking the CH2 output from one at the crystal frequency and using it as the crystal input to the other.  The isolation improved by on the order of 20 to 30 dB.  You can see it in the design

https://github.com/profdc9/VNA/tree/master/board-smt

So I think it is definitely a way to go if you have the pins available for two I2C connections.
 


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