EEVblog Electronics Community Forum
Electronics => RF, Microwave, Ham Radio => Topic started by: Noah on October 14, 2021, 12:11:28 pm
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I am working on an FPGA <-> FPGA link using the GTY transceivers in an Ultrascale+ Virtex FPGA. Two transceivers are connected through a QSFP direct attach copper cable of 1.5m length with ~15dbm insertion loss. Using the IBERT in the Xilinx FPGA I can measure a statistical eye diagram and change different settings of pre/post emphasis.
I noticed that the eye diagram gets worse if I enable either pre or post emphasis. The link has a line rate of 25Gbps and 390mVpp swing and DC coupling with floating 100E termination.
The Tx driver is documented in this PDF starting page 167.
https://www.xilinx.com/support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf (https://www.xilinx.com/support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf)
Can someone explain the observed effect to me or point me to some good resources on high speed serial links and why this might happen?
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Not an FPGA guy, but am a high-speed-serial guy - How do you train the equalization? Improper settings will make things worse, rather than better.
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The receivers have a DFE with discrete-time adaptive high-pass filter and AGC that continuously runs an MMSE adaptive algorithm (linked datasheet p. 197 ff). The data stream is scrambled so the DFE should have enough data to continuously be trained. I can reset the receiver and watch ~90 bit errors reported until the DFE settles and the BER goes to zero.
Could it be that at 25Gbps my cable just can't support the precursor? The datasheet:
https://www.molex.com/pdm_docs/ts/1002970003-000.pdf (https://www.molex.com/pdm_docs/ts/1002970003-000.pdf)
Does the transmitted signal with applied pre-curser have a faster rise time?
(https://i.ibb.co/7Nh5Whv/image.png) (https://ibb.co/S7S8nSN)
(https://i.ibb.co/QF6RTv0/image.png) (https://ibb.co/ccNHZhq)