CD4046 PLL with external VCO?

[Xnke]

Looking at another way of doing the GPSDO.

I have a GPS module that will output up to a 10mhz signal, but it's jittery. It's accurate, but jittery. There is less jitter when outputting 1Mhz than 10Mhz, as the internal clock runs at 48Mhz. (Ublox Neo-7M)

I have a box of OFC-McCoy 10Mhz OCXO modules, all of them OSC92-100B. They need a 0-8v control signal, and 12v power.

The thought is, instead of using a microcontroller to count and compare the two, why not phase lock them with the 4046, but instead of using the internal vco, use the 0-8v control voltage.

For one, the 4046 control voltage is probably tailored to the internal vco. Certainly, it's not going to go up to 8V, so some signal modification is gonna be needed. The microcontoller that will setup the GPS module on power up, and display relevant information on the 40x2 LCD, can do this.

Two, I can find no data in the datasheets, or application notes, of using this chip with an external VCO.

Has anyone done this, and if so, am I thinking down the right road by using the PLL2 style control, that maintains a 0* phase lock between the two inputs?

[Gyro]

Yes, I've done it, and it works well for the simplicity...  https://www.eevblog.com/forum/projects/my-u-blox-lea-6t-based-gpsdo-(very-scruffy-initial-breadboard-stage)/

Yes, you want to move away from 10MHz out from the GPS module - as you say, it is a non integer divide of the 48MHz clock. I tried at 1MHz (dividing down the 10MHz OCXO) but finally settled on using 100kHz into the 4046 (a single 74HC390 package will divide your OCXO down to 100kHz).

Phase comparator 1 (XOR) gives better results (best rejection of GPS module jitter and lock time) - there is no particular point in keeping 0' phase lock between the two inputs, 90' is fine.

BTW. In my schematic, I forgot to show that the 4046 pin 5 (INH) is tied high to disable the internal VCO. [EDIT, no I didn't].


P.S. Remember that the GPS module output needs to be set for 50:50 mark:space. The OCXO divider is automatically 50:50 as long as it's wired as shown (divide by 2 last).

[Xnke]

Interesting-if it wasn't for getting the GPS module configured on startup, I really wouldn't need the controller. Yours seems to work perfectly fine as-is.

So, pulling the microcontroller wizardry out of the picture-we'll get it back later.

Using the schematic for the divider and PLL, I'd have to use a different op-amp to kick the control voltage up to 0-8V, to cover the range of the OCXO. I'd probably skip right to the 100kHz PLL frequency, after reading your results, but I'd take the output from the 10Mhz OCXO directly and drive a distribution amplifier-ideally, I'd have both the 10Mhz and 5Mhz sine outputs.

I'll work this out in Eagle a bit later tonight and see what I can come up with.

[Gyro]

Yes, I was able to use mine 'as-is' once configured. If you look at the LEA-6T ebay module that I used (linked in my thread above, but https://www.eevblog.com/forum/projects/ebay-u-blox-lea-6t-gps-module-teardown-and-initial-test/ ), you can see that it has an EEPROM and battery backup for the internal config RAM. It ought to be possible for you to tack an EEPROM onto your 7M module (check the pinout) and store the defaults to it using u-Center.

My plan (if I ever do get around to boxing it) is just to have a USB socket on the front for configuration and monitoring purposes. Maybe I'll tack a micro and display onto the serial port line just to display time and status - I don't know yet, but it's an option.

If you use a CD4046 rather than HC4046 then it is good for a supply of up to 15V, so you shouldn't have any difficulty in powering it and the opamp at 8V to meet the control voltage range of your OCXO.


P.S. Out of curiosity, I just looked on ebay to see if those LEA-6T modules are still available. They are, but most are around £100   I'm sure I paid less than £20 a few years back! Maybe there are cheaper later module options in the sweet-spot these days. [EDIT: NEO-6M boards with EEPROM and battery look really cheap, but are not timing optimized].

[iMo]

..I have a GPS module that will output up to a 10mhz signal, but it's jittery. It's accurate, but jittery. There is less jitter when outputting 1Mhz than 10Mhz, as the internal clock runs at 48Mhz. (Ublox Neo-7M)

The 10MHz output on Neo-6/7/8 modules is broken (not "jittery") because you divide by "4.8"
12MHz, 8MHz, 6MHz, .. etc are "clean" with typical gps jitter.
Clean are all frequencies where Fout=48MHz/N, where N=4,5,6,7,8,9..

[David Hess]

..I have a GPS module that will output up to a 10mhz signal, but it's jittery. It's accurate, but jittery. There is less jitter when outputting 1Mhz than 10Mhz, as the internal clock runs at 48Mhz. (Ublox Neo-7M)

The 10MHz output on Neo-6/7/8 modules is broken (not "jittery") because you divide by "4.8"
12MHz, 8MHz, 6MHz, .. etc are "clean" with typical gps jitter.
Clean are all frequencies where Fout=48MHz/N, where N=4,5,6,7,8,9..

Unless the internal 48 MHz clock is phased locked to the GPS clock, there is jitter between them anyway no matter what the divider is.  This gets back to the whole "hanging bridge" issue named for the look of the phase error graph.  Once the loop bandwidth is reduced enough for good performance, the clock jitter can be ignored.  In practice the solution jitter can be ignored also because the loop bandwidth has to take the periodic solution error into account also.

The above makes me wonder that no timing receivers use a DDS output to produce a sine wave for timing but I guess that just kicks the can down the road.  Anybody who can limit their loop bandwidth to the GPS solution timing can handle a square wave with jitter just fine so there is no advantage.

Just to prevent any misunderstanding about the above, the 4046 PLL will work fine for this application but I think even better performance could be had with an all analog design which supports a longer time constant.

[Xnke]

74HC390 section is finished up, setup as a divide-by-100. The OXCO is an OFC-McCoy unit, and has a +9dBm 50ohm  sinewave output. I'm thinking some kind of signal shaping is going to be needed to convert it down to a TTL-compatible squarewave. Maybe just a single transistor will do the job, if not I've got a few NE592's that are definitely fast enough.

Maybe even just a diode clipper will do. I still need to send the 10Mhz sine through a distribution amp to push the 50 ohm output anyway, so what's another opamp in a convoluted mess?

[Xnke]

So the output of my OSC92-100B OXCO won't reliably trigger a 74HC-series logic gate without help. I figured this would be the case, as it's only 0.63v or so when loaded to 50R. I don't *need* to load it that much, but it still doesn't reliably trigger the gate, even at 150R termination.

So, I dug through my box of junk and found a handful of "ITS30419" dual transistor arrays-they're made for LTP's and I think they're Intersil Semiconductor, but I can't find any data on them. I got them down at Tanner Electronics when I was in dallas over new years.

I'm looking at this circuit for squaring and bringing the level up to 5v. Some breadboarding will be needed to see if I can power it from 8V and still get enough performance at 10Mhz to drive the divider properly.



Anyone have any info on the dual transistor arrays or using an LTP in a similiar squaring circuit?

[David Hess]

That or some variation of a comparator will certainly do it.  AC coupling into a CMOS stage biased into its linear region would also work.